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https://github.com/dolphin-emu/dolphin.git
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3fa198f208
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3911 8ced0084-cf51-0410-be5f-012b33b47a6e
119 lines
3.7 KiB
C++
119 lines
3.7 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#ifndef _ATOMIC_GCC_H_
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#define _ATOMIC_GCC_H_
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#include "Common.h"
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// Atomic operations are performed in a single step by the CPU. It is
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// impossible for other threads to see the operation "half-done."
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//
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// Some atomic operations can be combined with different types of memory
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// barriers called "Acquire semantics" and "Release semantics", defined below.
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//
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// Acquire semantics: Future memory accesses cannot be relocated to before the
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// operation.
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//
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// Release semantics: Past memory accesses cannot be relocated to after the
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// operation.
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//
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// These barriers affect not only the compiler, but also the CPU.
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namespace Common
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{
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inline void AtomicAdd(volatile u32& target, u32 value) {
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__sync_add_and_fetch(&target, value);
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}
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inline void AtomicAnd(volatile u32& target, u32 value) {
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__sync_and_and_fetch(&target, value);
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}
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inline void AtomicIncrement(volatile u32& target) {
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__sync_add_and_fetch(&target, 1);
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}
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inline u32 AtomicLoad(volatile u32& src) {
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return src; // 32-bit reads are always atomic.
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}
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inline u32 AtomicLoadAcquire(volatile u32& src) {
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__sync_synchronize(); // TODO: May not be necessary.
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return src;
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}
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inline void AtomicOr(volatile u32& target, u32 value) {
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__sync_or_and_fetch(&target, value);
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}
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inline void AtomicStore(volatile u32& dest, u32 value) {
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dest = value; // 32-bit writes are always atomic.
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}
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inline void AtomicStoreRelease(volatile u32& dest, u32 value) {
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__sync_lock_test_and_set(&dest, value); // TODO: Wrong! This function is has acquire semantics.
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}
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}
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// Old code kept here for reference in case we need the parts with __asm__ __volatile__.
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#if 0
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LONG SyncInterlockedIncrement(LONG *Dest)
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{
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#if defined(__GNUC__) && defined (__GNUC_MINOR__) && ((4 < __GNUC__) || (4 == __GNUC__ && 1 <= __GNUC_MINOR__))
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return __sync_add_and_fetch(Dest, 1);
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#else
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register int result;
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__asm__ __volatile__("lock; xadd %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (1), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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LONG SyncInterlockedExchangeAdd(LONG *Dest, LONG Val)
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{
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#if defined(__GNUC__) && defined (__GNUC_MINOR__) && ((4 < __GNUC__) || (4 == __GNUC__ && 1 <= __GNUC_MINOR__))
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return __sync_add_and_fetch(Dest, Val);
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#else
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register int result;
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__asm__ __volatile__("lock; xadd %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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LONG SyncInterlockedExchange(LONG *Dest, LONG Val)
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{
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#if defined(__GNUC__) && defined (__GNUC_MINOR__) && ((4 < __GNUC__) || (4 == __GNUC__ && 1 <= __GNUC_MINOR__))
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return __sync_lock_test_and_set(Dest, Val);
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#else
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register int result;
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__asm__ __volatile__("lock; xchg %0,%1"
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: "=r" (result), "=m" (*Dest)
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: "0" (Val), "m" (*Dest)
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: "memory");
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return result;
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#endif
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}
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#endif
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#endif
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