mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-15 05:47:56 -07:00
334 lines
7.5 KiB
Plaintext
334 lines
7.5 KiB
Plaintext
IROM_BASE: equ 0x8000
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lri $CR, #0x00ff
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lri $SR, #0x2000
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si @DMBH, #0x8071
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si @DMBL, #0xfeed
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mainloop:
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clr $ACC1
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clr $ACC0
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call wait_for_cpu_mbox+#IROM_BASE
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;mmem-addr
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param1:
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lr $AC1.M, @CMBL
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lri $AC0.M, #0xa001
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cmp
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jnz param2+#IROM_BASE
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call wait_for_cpu_mbox+#IROM_BASE
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lr $IX0, @CMBH
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lr $IX1, @CMBL
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jmp mainloop+#IROM_BASE
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;iram-addr
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param2:
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lri $AC0.M, #0xc002
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cmp
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jnz param3+#IROM_BASE
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call wait_for_cpu_mbox+#IROM_BASE
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lr $IX2, @CMBL
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jmp mainloop+#IROM_BASE
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;iram-length
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param3:
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lri $AC0.M, #0xa002
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cmp
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jnz param4+#IROM_BASE
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call wait_for_cpu_mbox+#IROM_BASE
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lr $IX3, @CMBL
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jmp mainloop+#IROM_BASE
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;dram-length
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param4:
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lri $AC0.M, #0xb002
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cmp
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jnz param5+#IROM_BASE
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call wait_for_cpu_mbox+#IROM_BASE
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lr $AX0.L, @CMBL
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jmp mainloop+#IROM_BASE
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;iram-start-addr
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param5:
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lri $AC0.M, #0xd001
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cmp
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jnz mainloop+#IROM_BASE
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call wait_for_cpu_mbox+#IROM_BASE
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lr $AR0, @CMBL
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; skip the branch of bootucode that uses the AX registers
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jmp bootucode_ix+#IROM_BASE
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wait_dma:
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lrs $AC0.M, @DSCR
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andcf $AC0.M, #0x0004
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jlz wait_dma+#IROM_BASE
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ret
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WARNPC 0x78
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ORG 0x78
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; called by GBA ucode
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wait_for_cpu_mbox:
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lrs $AC0.M, @CMBH
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andcf $AC0.M, #0x8000
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jlnz wait_for_cpu_mbox+#IROM_BASE
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ret
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WARNPC 0x7e
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ORG 0x7e
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; called by GBA ucode
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wait_for_dsp_mbox:
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lrs $AC0.M, @DMBH
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andcf $AC0.M, #0x8000
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jlz wait_for_dsp_mbox+#IROM_BASE
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ret
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WARNPC 0x8b
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ORG 0x8b
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; called by GBA ucode
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dram_to_cpu:
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sr @DSMAH, $AX0.H
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sr @DSMAL, $AX0.L
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si @DSCR, #0x1
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sr @DSPA, $AX1.H
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sr @DSBL, $AX1.L
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call wait_dma+#IROM_BASE
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ret
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WARNPC 0xb5
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ORG 0xb5
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bootucode:
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set16
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clr $ACC0
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mrr $AC0.M, $AX1.L
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andi $AC0.M, #0xffff
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jz bootucode_ix+#IROM_BASE
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WARNPC 0xbc
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ORG 0xbc
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; called by GBA ucode
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bootucode_ax:
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lris $AC0.M, #0
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srs @DSCR, $AC0.M
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sr @DSMAH, $AX0.H
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sr @DSMAL, $AX0.L
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sr @DSPA, $AX1.H
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sr @DSBL, $AX1.L
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call wait_dma+#IROM_BASE
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bootucode_ix:
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mrr $AC0.M, $IX3
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andi $AC0.M, #0xffff
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jz bootucode_epilogue+#IROM_BASE
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lris $AC0.M, #0x2
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srs @DSCR, $AC0.M
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sr @DSMAH, $IX0
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sr @DSMAL, $IX1
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sr @DSPA, $IX2
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sr @DSBL, $IX3
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call wait_dma+#IROM_BASE
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bootucode_epilogue:
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clr $ACC1
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lr $AC1.M, @DSBL
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jmpr $AR0
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WARNPC 0xe7
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ORG 0xe7
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; Args:
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; AR0 points to the 32 input 1 samples (s16)
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; AR1 points to the volume data (init1, delta1, init2, delta2)
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; AR2 points to the already mixed samples for output 1 (s32)
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; AR3 points to where the output 1 should be stored (s32)
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; IX0 points to the 32 input 2 samples (s16)
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; IX1 points to where the output 2 should be stored (s32)
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;
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; Returns:
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; AX0.L is the value of the last sample from input 1
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; AX1.H is the value of the last sample from input 2
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;
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; for i = 0..31:
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; ar3[i] = ((ar2[i] << 16) + ar0[i] * ar1[0]) >> 16
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; for i = 0..31:
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; ix1[i] = ((ix1[i] << 16) + ix0[i] * ar1[2]) >> 16
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; ax0.l = ar0[31] * ar1[0]
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; ax1.h = ix0[31] * ar1[2]
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mix_two_add:
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call mix_add+#IROM_BASE
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mrr $AR0, $IX0
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mrr $AR2, $IX1
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mrr $AR3, $IX1
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mrr $IX0, $AX0.L
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call mix_add+#IROM_BASE
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mrr $AX1.H, $AX0.L
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mrr $AX0.L, $IX0
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ret
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WARNPC 0x1f4
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ORG 0x1f4
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; used by GBA ucode for joyboot length and is the end of some mixing function
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; (for an example of hitting the full function, try running the main menu of
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; Metroid Prime using the Nintendo DSP ROM).
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sub_81f4:
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asr16'ir $ACC1 : $AR1
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clr's $ACC0 : @$AR3, $AC1.M ; AC1.M is always #0x0 here.
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; necessary both to match register state of official ROM, and for the
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; following mul. could also be mrr $AX1.H, $AC0.M (before clearing ACC0).
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mrr $AX1.H, $AX0.H
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; make the product register match.
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mul's $AX1.L, $AX1.H : @$AR3, $AC1.L
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ret
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WARNPC 0x1f9
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ORG 0x1f9
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; Args:
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; AR0 points to the 32 input samples (s16)
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; AR1 points to the volume data (init, delta)
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; AR2 points to the already mixed samples (s32)
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; AR3 points to where the output should be stored (s32)
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;
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; Returns:
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; AX0.L is the value of the last sample
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; AX1.H is the first address after the output
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;
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; for i = 0..31:
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; ar3[i] = ((ar2[i] << 16) + ar0[i] * ar1[0]) >> 16
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; ax0.l = ar0[31] * ar1[0]
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; ax1.h = ar3 + 32 // assuming ar3 is a s32 pointer
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mix_add:
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lrri $AX1.L, @$AR1
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iar $AR1
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bloopi #32, ____mix_add_end_loop+#IROM_BASE
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lrri $AC0.M, @$AR2
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lrri $AC0.L, @$AR2
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lsl16 $ACC0
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lrri $AX0.H, @$AR0
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mulx $AX0.H, $AX1.L
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addp $ACC0
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asr16 $ACC0
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srri @$AR3, $AC0.M
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____mix_add_end_loop:
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srri @$AR3, $AC0.L
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movp $ACC0
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mrr $AX0.L, $AC0.M
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mrr $AX1.H, $AR3
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ret
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WARNPC 0x282
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ORG 0x282
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; for i = 0..31:
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; ar3[i] = ar1[0] + i * ar1[1]
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; ar2[i] = ((ar2[i] << 16) + ar0[i] * ar3[i]) >> 16
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; ar3[i+32] = ar1[2] + i * ar1[3]
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; ix1[i] = ((ix1[i] << 16) + ix0[i] * ar3[i+32]) >> 16
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; ax0.l = ar0[31] * ar3[31]
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; ax1.h = ix0[31] * ar3[63]
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mix_two_add_ramp:
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call mix_add_ramp+#IROM_BASE
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mrr $AR0, $IX0
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mrr $AR2, $IX1
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mrr $IX1, $AX0.L
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call mix_add_ramp+#IROM_BASE
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mrr $AX1.H, $AX0.L
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mrr $AX0.L, $IX1
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ret
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WARNPC 0x458
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ORG 0x458
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; used by GBA ucode for joyboot length
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sub_8458:
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; AC1.L after = AC1.M before + 7. this looks really stupid, but matches
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; captured traces and seems to work.
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addis $AC1.M, #0x7
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asr16 $ACC1
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srri @$AR3, $AC1.M ; or just #0x0.
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srri @$AR3, $AC1.L
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ret
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WARNPC 0x45d
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ORG 0x45d
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; for i = 0..31:
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; ar3[i] = ar1[0] + i * ar1[1]
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; ar2[i] = ((ar2[i] << 16) + ar0[i] * ar3[i]) >> 16
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; ax0.l = ar0[31] * ar3[31]
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mix_add_ramp:
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clr $ACC0
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clr $ACC1
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lrri $AC0.L, @$AR1
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lrrd $AC1.L, @$AR1
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mrr $IX2, $AR3
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bloopi #32, ____mix_add_ramp_end_ramp+#IROM_BASE
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srri @$AR3, $AC0.L
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____mix_add_ramp_end_ramp:
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add $ACC0, $ACC1
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srri @$AR1, $AC0.L
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iar $AR1
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mrr $IX3, $AR1
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mrr $AR1, $IX2
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mrr $AR3, $AR2
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bloopi #32, ____mix_add_ramp_end_loop+#IROM_BASE
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lrri $AC0.M, @$AR2
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lrri $AC0.L, @$AR2
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lsl16 $ACC0
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lrri $AX0.H, @$AR0
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lrri $AX1.L, @$AR1
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mulx $AX0.H, $AX1.L
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addp $ACC0
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asr16 $ACC0
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srri @$AR3, $AC0.M
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____mix_add_ramp_end_loop:
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srri @$AR3, $AC0.L
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movp $ACC0
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mrr $AX0.L, $AC0.M
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mrr $AR1, $IX3
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mrr $AR3, $IX2
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ret
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WARNPC 0x723
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ORG 0x723
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; called by GBA ucode
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sub_8723:
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; in GBA-HLE, the nonce challenge is XOR'd with 0x6f646573, which happens
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; to match the values of the AX1.H register across these two calls.
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xorr $AC1.M, $AX1.H
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; the value of @AR2 is always the same as AC1.M after
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srrd @$AR2, $AC1.M
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ret
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WARNPC 0x809
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ORG 0x809
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; called by GBA ucode
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sub_8809:
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; AR2 is the only addressing register that corresponds to the dmem writes
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; could be AC1.L or AX0.L in the second call, but can't be AX0.L in the
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; third call.
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srr @$AR2, $AC1.L
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; AC1.M after calling always look like either AC1.M | AC0.M or
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; AC1.M | AX0.H. TODO: Why pick AX0.H?
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orr $AC1.M, $AX0.H
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; the second dmem write is incremented only in calls #3A and #3B. There,
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; IX2 is the only register set to 1, and it's specifically set to 1 in the
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; ucode. It's set to 0 in the first two calls.
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addarn $AR2, $IX2
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; obvious
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srri @$AR2, $AC1.M
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ret
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WARNPC 0x8e5
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ORG 0x8e5
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; used by GBA ucode for challenge nonce, logo palette/speed, and joyboot length
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sub_88e5:
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dar $AR1 ; always gets decremented, no effect on rest of function
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lrri $AC1.M, @$AR2
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lrrd $AC1.L, @$AR2
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add $ACC0, $ACC1 ; signed addition
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orr $AC0.M, $AX0.H
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srri @$AR2, $AC0.M
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srr @$AR2, $AC0.L
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ret
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WARNPC 0x1000
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ORG 0x1000
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