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https://github.com/dolphin-emu/dolphin.git
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756 lines
19 KiB
C++
756 lines
19 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id: dis_groups.cc 11885 2013-10-15 17:19:18Z sshwarts $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2005-2011 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#include <stdio.h>
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#include <assert.h>
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#include "disasm.h"
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/*
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#if BX_DEBUGGER
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#include "../bx_debug/debug.h"
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#endif
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*/
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void disassembler::Apw(const x86_insn *insn)
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{
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Bit16u imm16 = fetch_word();
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Bit16u cs_selector = fetch_word();
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dis_sprintf("0x%04x:%04x", (unsigned) cs_selector, (unsigned) imm16);
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}
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void disassembler::Apd(const x86_insn *insn)
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{
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Bit32u imm32 = fetch_dword();
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Bit16u cs_selector = fetch_word();
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dis_sprintf("0x%04x:%08x", (unsigned) cs_selector, (unsigned) imm32);
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}
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// 8-bit general purpose registers
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void disassembler::AL_Reg(const x86_insn *insn) { dis_sprintf("%s", general_8bit_regname[rAX_REG]); }
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void disassembler::CL_Reg(const x86_insn *insn) { dis_sprintf("%s", general_8bit_regname[rCX_REG]); }
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// 16-bit general purpose registers
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void disassembler::AX_Reg(const x86_insn *insn) {
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dis_sprintf("%s", general_16bit_regname[rAX_REG]);
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}
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void disassembler::DX_Reg(const x86_insn *insn) {
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dis_sprintf("%s", general_16bit_regname[rDX_REG]);
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}
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// 32-bit general purpose registers
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void disassembler::EAX_Reg(const x86_insn *insn)
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{
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dis_sprintf("%s", general_32bit_regname[rAX_REG]);
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}
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// 64-bit general purpose registers
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void disassembler::RAX_Reg(const x86_insn *insn)
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{
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dis_sprintf("%s", general_64bit_regname[rAX_REG]);
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}
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void disassembler::RCX_Reg(const x86_insn *insn)
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{
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dis_sprintf("%s", general_64bit_regname[rCX_REG]);
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}
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// segment registers
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void disassembler::CS(const x86_insn *insn) { dis_sprintf("%s", segment_name[CS_REG]); }
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void disassembler::DS(const x86_insn *insn) { dis_sprintf("%s", segment_name[DS_REG]); }
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void disassembler::ES(const x86_insn *insn) { dis_sprintf("%s", segment_name[ES_REG]); }
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void disassembler::SS(const x86_insn *insn) { dis_sprintf("%s", segment_name[SS_REG]); }
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void disassembler::FS(const x86_insn *insn) { dis_sprintf("%s", segment_name[FS_REG]); }
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void disassembler::GS(const x86_insn *insn) { dis_sprintf("%s", segment_name[GS_REG]); }
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void disassembler::Sw(const x86_insn *insn) { dis_sprintf("%s", segment_name[insn->nnn]); }
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// control register
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void disassembler::Cd(const x86_insn *insn)
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{
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if (intel_mode)
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dis_sprintf ("cr%d", insn->nnn);
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else
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dis_sprintf("%%cr%d", insn->nnn);
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}
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void disassembler::Cq(const x86_insn *insn) { Cd(insn); }
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// debug register
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void disassembler::Dd(const x86_insn *insn)
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{
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if (intel_mode)
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dis_sprintf ("dr%d", insn->nnn);
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else
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dis_sprintf("%%dr%d", insn->nnn);
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}
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void disassembler::Dq(const x86_insn *insn) { Dd(insn); }
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// 8-bit general purpose register
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void disassembler::Reg8(const x86_insn *insn)
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{
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unsigned reg = (insn->b1 & 7) | insn->rex_b;
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if (reg < 4 || insn->extend8b)
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dis_sprintf("%s", general_8bit_regname_rex[reg]);
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else
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dis_sprintf("%s", general_8bit_regname[reg]);
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}
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// 16-bit general purpose register
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void disassembler::RX(const x86_insn *insn)
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{
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dis_sprintf("%s", general_16bit_regname[(insn->b1 & 7) | insn->rex_b]);
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}
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// 32-bit general purpose register
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void disassembler::ERX(const x86_insn *insn)
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{
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dis_sprintf("%s", general_32bit_regname[(insn->b1 & 7) | insn->rex_b]);
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}
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// 64-bit general purpose register
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void disassembler::RRX(const x86_insn *insn)
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{
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dis_sprintf("%s", general_64bit_regname[(insn->b1 & 7) | insn->rex_b]);
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}
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// general purpose register or memory operand
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void disassembler::Eb(const x86_insn *insn)
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{
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if (insn->mod == 3) {
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if (insn->rm < 4 || insn->extend8b)
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dis_sprintf("%s", general_8bit_regname_rex[insn->rm]);
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else
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dis_sprintf("%s", general_8bit_regname[insn->rm]);
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}
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else
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(this->*resolve_modrm)(insn, B_SIZE);
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}
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void disassembler::Ew(const x86_insn *insn)
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{
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if (insn->mod == 3)
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dis_sprintf("%s", general_16bit_regname[insn->rm]);
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else
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(this->*resolve_modrm)(insn, W_SIZE);
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}
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void disassembler::Ed(const x86_insn *insn)
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{
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if (insn->mod == 3)
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dis_sprintf("%s", general_32bit_regname[insn->rm]);
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else
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(this->*resolve_modrm)(insn, D_SIZE);
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}
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void disassembler::Eq(const x86_insn *insn)
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{
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if (insn->mod == 3)
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dis_sprintf("%s", general_64bit_regname[insn->rm]);
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else
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(this->*resolve_modrm)(insn, Q_SIZE);
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}
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void disassembler::Ey(const x86_insn *insn)
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{
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if (insn->os_64) Eq(insn);
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else Ed(insn);
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}
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void disassembler::Ebd(const x86_insn *insn)
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{
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if (insn->mod == 3)
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dis_sprintf("%s", general_32bit_regname[insn->rm]);
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else
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(this->*resolve_modrm)(insn, B_SIZE);
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}
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void disassembler::Ewd(const x86_insn *insn)
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{
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if (insn->mod == 3)
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dis_sprintf("%s", general_32bit_regname[insn->rm]);
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else
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(this->*resolve_modrm)(insn, W_SIZE);
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}
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// general purpose register
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void disassembler::Gb(const x86_insn *insn)
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{
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if (insn->nnn < 4 || insn->extend8b)
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dis_sprintf("%s", general_8bit_regname_rex[insn->nnn]);
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else
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dis_sprintf("%s", general_8bit_regname[insn->nnn]);
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}
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void disassembler::Gw(const x86_insn *insn)
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{
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dis_sprintf("%s", general_16bit_regname[insn->nnn]);
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}
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void disassembler::Gd(const x86_insn *insn)
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{
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dis_sprintf("%s", general_32bit_regname[insn->nnn]);
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}
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void disassembler::Gq(const x86_insn *insn)
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{
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dis_sprintf("%s", general_64bit_regname[insn->nnn]);
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}
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void disassembler::Gy(const x86_insn *insn)
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{
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if (insn->os_64) Gq(insn);
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else Gd(insn);
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}
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// vex encoded general purpose register
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void disassembler::By(const x86_insn *insn)
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{
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if (insn->os_64)
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dis_sprintf("%s", general_64bit_regname[insn->vex_vvv]);
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else
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dis_sprintf("%s", general_32bit_regname[insn->vex_vvv]);
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}
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// immediate
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void disassembler::I1(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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dis_putc ('1');
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}
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void disassembler::Ib(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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dis_sprintf("0x%02x", (unsigned) fetch_byte());
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}
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void disassembler::Iw(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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dis_sprintf("0x%04x", (unsigned) fetch_word());
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}
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void disassembler::IbIb(const x86_insn *insn)
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{
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Bit8u ib1 = fetch_byte();
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Bit8u ib2 = fetch_byte();
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if (intel_mode) {
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dis_sprintf("0x%02x, 0x%02x", ib1, ib2);
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}
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else {
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dis_sprintf("$0x%02x, $0x%02x", ib2, ib1);
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}
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}
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void disassembler::IwIb(const x86_insn *insn)
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{
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Bit16u iw = fetch_word();
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Bit8u ib = fetch_byte();
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if (intel_mode) {
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dis_sprintf("0x%04x, 0x%02x", iw, ib);
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}
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else {
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dis_sprintf("$0x%02x, $0x%04x", ib, iw);
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}
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}
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void disassembler::Id(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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dis_sprintf("0x%08x", (unsigned) fetch_dword());
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}
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void disassembler::Iq(const x86_insn *insn)
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{
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Bit64u value = fetch_qword();
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if (! intel_mode) dis_putc('$');
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dis_sprintf("0x%08x%08x", GET32H(value), GET32L(value));
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}
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// sign extended immediate
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void disassembler::sIbw(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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Bit16u imm16 = (Bit8s) fetch_byte();
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dis_sprintf("0x%04x", (unsigned) imm16);
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}
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// sign extended immediate
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void disassembler::sIbd(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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Bit32u imm32 = (Bit8s) fetch_byte();
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dis_sprintf ("0x%08x", (unsigned) imm32);
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}
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// sign extended immediate
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void disassembler::sIbq(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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Bit64u imm64 = (Bit8s) fetch_byte();
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dis_sprintf ("0x%08x%08x", GET32H(imm64), GET32L(imm64));
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}
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// sign extended immediate
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void disassembler::sIdq(const x86_insn *insn)
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{
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if (! intel_mode) dis_putc('$');
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Bit64u imm64 = (Bit32s) fetch_dword();
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dis_sprintf ("0x%08x%08x", GET32H(imm64), GET32L(imm64));
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}
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// floating point
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void disassembler::ST0(const x86_insn *insn)
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{
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if (intel_mode)
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dis_sprintf ("st(0)");
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else
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dis_sprintf("%%st(0)");
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}
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void disassembler::STi(const x86_insn *insn)
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{
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if (intel_mode)
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dis_sprintf ("st(%d)", insn->rm & 7);
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else
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dis_sprintf("%%st(%d)", insn->rm & 7);
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}
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// 16-bit general purpose register
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void disassembler::Rw(const x86_insn *insn)
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{
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dis_sprintf("%s", general_16bit_regname[insn->rm]);
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}
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// 32-bit general purpose register
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void disassembler::Rd(const x86_insn *insn)
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{
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dis_sprintf("%s", general_32bit_regname[insn->rm]);
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}
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// 64-bit general purpose register
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void disassembler::Rq(const x86_insn *insn)
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{
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dis_sprintf("%s", general_64bit_regname[insn->rm]);
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}
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void disassembler::Ry(const x86_insn *insn)
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{
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if (insn->os_64) Rq(insn);
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else Rd(insn);
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}
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// mmx register
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void disassembler::Pq(const x86_insn *insn)
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{
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if (intel_mode)
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dis_sprintf ("mm%d", insn->nnn & 0x7);
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else
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dis_sprintf("%%mm%d", insn->nnn & 0x7);
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}
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void disassembler::Nq(const x86_insn *insn)
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{
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if (intel_mode)
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dis_sprintf ("mm%d", insn->rm & 0x7);
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else
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dis_sprintf("%%mm%d", insn->rm & 0x7);
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}
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void disassembler::Qd(const x86_insn *insn)
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{
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if (insn->mod == 3)
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{
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if (intel_mode)
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dis_sprintf ("mm%d", insn->rm & 0x7);
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else
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dis_sprintf("%%mm%d", insn->rm & 0x7);
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}
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else
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(this->*resolve_modrm)(insn, D_SIZE);
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}
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void disassembler::Qq(const x86_insn *insn)
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{
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if (insn->mod == 3)
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{
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if (intel_mode)
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dis_sprintf ("mm%d", insn->rm & 0x7);
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else
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dis_sprintf("%%mm%d", insn->rm & 0x7);
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}
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else
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(this->*resolve_modrm)(insn, Q_SIZE);
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}
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// xmm/ymm register
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void disassembler::Udq(const x86_insn *insn)
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{
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dis_sprintf("%s%d", vector_reg_name[insn->vex_l], insn->rm);
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}
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void disassembler::Ups(const x86_insn *insn) { Udq(insn); }
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void disassembler::Upd(const x86_insn *insn) { Udq(insn); }
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void disassembler::Uq(const x86_insn *insn) { Udq(insn); }
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void disassembler::Vq(const x86_insn *insn)
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{
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dis_sprintf("%s%d", vector_reg_name[insn->vex_l], insn->nnn);
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}
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void disassembler::Vdq(const x86_insn *insn) { Vq(insn); }
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void disassembler::Vss(const x86_insn *insn) { Vq(insn); }
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void disassembler::Vsd(const x86_insn *insn) { Vq(insn); }
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void disassembler::Vps(const x86_insn *insn) { Vq(insn); }
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void disassembler::Vpd(const x86_insn *insn) { Vq(insn); }
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void disassembler::VIb(const x86_insn *insn)
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{
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unsigned vreg = fetch_byte() >> 4;
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if (! insn->is_64) vreg &= 7;
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dis_sprintf("%s%d", vector_reg_name[insn->vex_l], vreg);
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}
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void disassembler::Hdq(const x86_insn *insn)
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{
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dis_sprintf("%s%d", vector_reg_name[insn->vex_l], insn->vex_vvv);
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}
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void disassembler::Hps(const x86_insn *insn) { Hdq(insn); }
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void disassembler::Hpd(const x86_insn *insn) { Hdq(insn); }
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void disassembler::Hss(const x86_insn *insn) { Hdq(insn); }
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void disassembler::Hsd(const x86_insn *insn) { Hdq(insn); }
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void disassembler::Wb(const x86_insn *insn)
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{
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if (insn->mod == 3) Udq(insn);
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else
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(this->*resolve_modrm)(insn, B_SIZE);
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}
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void disassembler::Ww(const x86_insn *insn)
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{
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if (insn->mod == 3) Udq(insn);
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else
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(this->*resolve_modrm)(insn, W_SIZE);
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}
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void disassembler::Wd(const x86_insn *insn)
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{
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if (insn->mod == 3) Udq(insn);
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else
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(this->*resolve_modrm)(insn, D_SIZE);
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}
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void disassembler::Wq(const x86_insn *insn)
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{
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if (insn->mod == 3) Udq(insn);
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else
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(this->*resolve_modrm)(insn, Q_SIZE);
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}
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void disassembler::Wdq(const x86_insn *insn)
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{
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if (insn->mod == 3) Udq(insn);
|
|
else
|
|
(this->*resolve_modrm)(insn, XMM_SIZE + insn->vex_l);
|
|
}
|
|
|
|
void disassembler::Wsd(const x86_insn *insn) { Wq(insn); }
|
|
void disassembler::Wss(const x86_insn *insn) { Wd(insn); }
|
|
void disassembler::Wpd(const x86_insn *insn) { Wdq(insn); }
|
|
void disassembler::Wps(const x86_insn *insn) { Wdq(insn); }
|
|
|
|
// direct memory access
|
|
void disassembler::OP_O(const x86_insn *insn, unsigned size)
|
|
{
|
|
const char *seg;
|
|
|
|
if (insn->is_seg_override())
|
|
seg = segment_name[insn->seg_override];
|
|
else
|
|
seg = segment_name[DS_REG];
|
|
|
|
print_datasize(size);
|
|
|
|
if (insn->as_64) {
|
|
Bit64u imm64 = fetch_qword();
|
|
dis_sprintf("%s:0x%08x%08x", seg, GET32H(imm64), GET32L(imm64));
|
|
}
|
|
else if (insn->as_32) {
|
|
Bit32u imm32 = fetch_dword();
|
|
dis_sprintf("%s:0x%08x", seg, (unsigned) imm32);
|
|
}
|
|
else {
|
|
Bit16u imm16 = fetch_word();
|
|
dis_sprintf("%s:0x%04x", seg, (unsigned) imm16);
|
|
}
|
|
}
|
|
|
|
void disassembler::Ob(const x86_insn *insn) { OP_O(insn, B_SIZE); }
|
|
void disassembler::Ow(const x86_insn *insn) { OP_O(insn, W_SIZE); }
|
|
void disassembler::Od(const x86_insn *insn) { OP_O(insn, D_SIZE); }
|
|
void disassembler::Oq(const x86_insn *insn) { OP_O(insn, Q_SIZE); }
|
|
|
|
// memory operand
|
|
void disassembler::OP_M(const x86_insn *insn, unsigned size)
|
|
{
|
|
if(insn->mod == 3)
|
|
dis_sprintf("(bad)");
|
|
else
|
|
(this->*resolve_modrm)(insn, size);
|
|
}
|
|
|
|
void disassembler::Ma(const x86_insn *insn) { OP_M(insn, X_SIZE); }
|
|
void disassembler::Mp(const x86_insn *insn) { OP_M(insn, X_SIZE); }
|
|
void disassembler::Ms(const x86_insn *insn) { OP_M(insn, X_SIZE); }
|
|
void disassembler::Mx(const x86_insn *insn) { OP_M(insn, X_SIZE); }
|
|
|
|
void disassembler::Mb(const x86_insn *insn) { OP_M(insn, B_SIZE); }
|
|
void disassembler::Mw(const x86_insn *insn) { OP_M(insn, W_SIZE); }
|
|
void disassembler::Md(const x86_insn *insn) { OP_M(insn, D_SIZE); }
|
|
void disassembler::Mq(const x86_insn *insn) { OP_M(insn, Q_SIZE); }
|
|
void disassembler::Mt(const x86_insn *insn) { OP_M(insn, T_SIZE); }
|
|
|
|
void disassembler::Mdq(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_l); }
|
|
void disassembler::Mps(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_l); }
|
|
void disassembler::Mpd(const x86_insn *insn) { OP_M(insn, XMM_SIZE + insn->vex_l); }
|
|
void disassembler::Mss(const x86_insn *insn) { OP_M(insn, D_SIZE); }
|
|
void disassembler::Msd(const x86_insn *insn) { OP_M(insn, Q_SIZE); }
|
|
|
|
// gather VSib
|
|
void disassembler::VSib(const x86_insn *insn)
|
|
{
|
|
if(insn->mod == 3)
|
|
dis_sprintf("(bad)");
|
|
else
|
|
(this->*resolve_modrm)(insn, (XMM_SIZE + insn->vex_l) | VSIB_Index);
|
|
}
|
|
|
|
// string instructions
|
|
void disassembler::OP_X(const x86_insn *insn, unsigned size)
|
|
{
|
|
const char *rsi, *seg;
|
|
|
|
if (insn->as_64) {
|
|
rsi = general_64bit_regname[rSI_REG];
|
|
}
|
|
else {
|
|
if (insn->as_32)
|
|
rsi = general_32bit_regname[rSI_REG];
|
|
else
|
|
rsi = general_16bit_regname[rSI_REG];
|
|
}
|
|
|
|
if (insn->is_seg_override())
|
|
seg = segment_name[insn->seg_override];
|
|
else
|
|
seg = segment_name[DS_REG];
|
|
|
|
print_datasize(size);
|
|
|
|
if (intel_mode)
|
|
dis_sprintf("%s:[%s]", seg, rsi);
|
|
else
|
|
dis_sprintf("%s:(%s)", seg, rsi);
|
|
}
|
|
|
|
void disassembler::Xb(const x86_insn *insn) { OP_X(insn, B_SIZE); }
|
|
void disassembler::Xw(const x86_insn *insn) { OP_X(insn, W_SIZE); }
|
|
void disassembler::Xd(const x86_insn *insn) { OP_X(insn, D_SIZE); }
|
|
void disassembler::Xq(const x86_insn *insn) { OP_X(insn, Q_SIZE); }
|
|
|
|
void disassembler::OP_Y(const x86_insn *insn, unsigned size)
|
|
{
|
|
const char *rdi;
|
|
|
|
if (insn->as_64) {
|
|
rdi = general_64bit_regname[rDI_REG];
|
|
}
|
|
else {
|
|
if (insn->as_32)
|
|
rdi = general_32bit_regname[rDI_REG];
|
|
else
|
|
rdi = general_16bit_regname[rDI_REG];
|
|
}
|
|
|
|
print_datasize(size);
|
|
|
|
if (intel_mode)
|
|
dis_sprintf("%s:[%s]", segment_name[ES_REG], rdi);
|
|
else
|
|
dis_sprintf("%s:(%s)", segment_name[ES_REG], rdi);
|
|
}
|
|
|
|
void disassembler::Yb(const x86_insn *insn) { OP_Y(insn, B_SIZE); }
|
|
void disassembler::Yw(const x86_insn *insn) { OP_Y(insn, W_SIZE); }
|
|
void disassembler::Yd(const x86_insn *insn) { OP_Y(insn, D_SIZE); }
|
|
void disassembler::Yq(const x86_insn *insn) { OP_Y(insn, Q_SIZE); }
|
|
|
|
void disassembler::OP_sY(const x86_insn *insn, unsigned size)
|
|
{
|
|
const char *rdi, *seg;
|
|
|
|
if (insn->as_64) {
|
|
rdi = general_64bit_regname[rDI_REG];
|
|
}
|
|
else {
|
|
if (insn->as_32)
|
|
rdi = general_32bit_regname[rDI_REG];
|
|
else
|
|
rdi = general_16bit_regname[rDI_REG];
|
|
}
|
|
|
|
print_datasize(size);
|
|
|
|
if (insn->is_seg_override())
|
|
seg = segment_name[insn->seg_override];
|
|
else
|
|
seg = segment_name[DS_REG];
|
|
|
|
if (intel_mode)
|
|
dis_sprintf("%s:[%s]", seg, rdi);
|
|
else
|
|
dis_sprintf("%s:(%s)", seg, rdi);
|
|
}
|
|
|
|
void disassembler::sYq(const x86_insn *insn) { OP_sY(insn, Q_SIZE); }
|
|
void disassembler::sYdq(const x86_insn *insn) { OP_sY(insn, XMM_SIZE + insn->vex_l); }
|
|
|
|
#define BX_JUMP_TARGET_NOT_REQ ((bx_address)(-1))
|
|
|
|
// jump offset
|
|
void disassembler::Jb(const x86_insn *insn)
|
|
{
|
|
Bit8s imm8 = (Bit8s) fetch_byte();
|
|
|
|
if (insn->is_64) {
|
|
Bit64u imm64 = (Bit8s) imm8;
|
|
|
|
if (offset_mode_hex) {
|
|
dis_sprintf(".+0x%08x%08x", GET32H(imm64), GET32L(imm64));
|
|
}
|
|
else {
|
|
dis_sprintf(".%+d", (int) imm8);
|
|
}
|
|
|
|
if (db_cs_base != BX_JUMP_TARGET_NOT_REQ) {
|
|
Bit64u target = db_eip + imm64;
|
|
target += db_cs_base;
|
|
dis_sprintf(" (0x%08x%08x)", GET32H(target), GET32L(target));
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (insn->os_32) {
|
|
Bit32u imm32 = (Bit8s) imm8;
|
|
|
|
if (offset_mode_hex) {
|
|
dis_sprintf(".+0x%08x", (unsigned) imm32);
|
|
}
|
|
else {
|
|
dis_sprintf(".%+d", (int) imm8);
|
|
}
|
|
|
|
if (db_cs_base != BX_JUMP_TARGET_NOT_REQ) {
|
|
Bit32u target = (Bit32u)(db_cs_base + db_eip + (Bit32s) imm32);
|
|
dis_sprintf(" (0x%08x)", target);
|
|
}
|
|
}
|
|
else {
|
|
Bit16u imm16 = (Bit8s) imm8;
|
|
|
|
if (offset_mode_hex) {
|
|
dis_sprintf(".+0x%04x", (unsigned) imm16);
|
|
}
|
|
else {
|
|
dis_sprintf(".%+d", (int) imm8);
|
|
}
|
|
|
|
if (db_cs_base != BX_JUMP_TARGET_NOT_REQ) {
|
|
Bit16u target = (Bit16u)((db_eip + (Bit16s) imm16) & 0xffff);
|
|
dis_sprintf(" (0x%08x)", target + db_cs_base);
|
|
}
|
|
}
|
|
}
|
|
|
|
void disassembler::Jw(const x86_insn *insn)
|
|
{
|
|
// Jw supported in 16-bit mode only
|
|
assert(! insn->is_64);
|
|
|
|
Bit16s imm16 = (Bit16s) fetch_word();
|
|
|
|
if (offset_mode_hex) {
|
|
dis_sprintf(".+0x%04x", (unsigned) (Bit16u) imm16);
|
|
}
|
|
else {
|
|
dis_sprintf(".%+d", (int) imm16);
|
|
}
|
|
|
|
if (db_cs_base != BX_JUMP_TARGET_NOT_REQ) {
|
|
Bit16u target = (db_eip + imm16) & 0xffff;
|
|
dis_sprintf(" (0x%08x)", target + db_cs_base);
|
|
}
|
|
}
|
|
|
|
void disassembler::Jd(const x86_insn *insn)
|
|
{
|
|
Bit32s imm32 = (Bit32s) fetch_dword();
|
|
|
|
if (insn->is_64) {
|
|
Bit64u imm64 = (Bit32s) imm32;
|
|
|
|
if (offset_mode_hex) {
|
|
dis_sprintf(".+0x%08x%08x", GET32H(imm64), GET32L(imm64));
|
|
}
|
|
else {
|
|
dis_sprintf(".%+d", (int) imm32);
|
|
}
|
|
|
|
if (db_cs_base != BX_JUMP_TARGET_NOT_REQ) {
|
|
Bit64u target = db_cs_base + db_eip + (Bit64s) imm64;
|
|
dis_sprintf(" (0x%08x%08x)", GET32H(target), GET32L(target));
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (offset_mode_hex) {
|
|
dis_sprintf(".+0x%08x", (unsigned) imm32);
|
|
}
|
|
else {
|
|
dis_sprintf(".%+d", (int) imm32);
|
|
}
|
|
|
|
if (db_cs_base != BX_JUMP_TARGET_NOT_REQ) {
|
|
Bit32u target = (Bit32u)(db_cs_base + db_eip + (Bit32s) imm32);
|
|
dis_sprintf(" (0x%08x)", target);
|
|
}
|
|
}
|