mirror of
https://github.com/dolphin-emu/dolphin.git
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558 lines
19 KiB
C++
558 lines
19 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include <atomic>
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#include <cstring>
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#include "Common/Assert.h"
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#include "Common/Atomic.h"
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#include "Common/ChunkFile.h"
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#include "Common/CommonTypes.h"
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#include "Common/Flag.h"
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#include "Common/Logging/Log.h"
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#include "Core/ConfigManager.h"
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#include "Core/CoreTiming.h"
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#include "Core/HW/GPFifo.h"
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#include "Core/HW/MMIO.h"
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#include "Core/HW/ProcessorInterface.h"
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#include "VideoCommon/CommandProcessor.h"
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#include "VideoCommon/Fifo.h"
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namespace CommandProcessor
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{
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static CoreTiming::EventType* et_UpdateInterrupts;
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// TODO(ector): Warn on bbox read/write
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// STATE_TO_SAVE
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SCPFifoStruct fifo;
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static UCPStatusReg m_CPStatusReg;
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static UCPCtrlReg m_CPCtrlReg;
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static UCPClearReg m_CPClearReg;
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static u16 m_bboxleft;
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static u16 m_bboxtop;
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static u16 m_bboxright;
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static u16 m_bboxbottom;
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static u16 m_tokenReg;
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static Common::Flag s_interrupt_set;
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static Common::Flag s_interrupt_waiting;
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static bool IsOnThread()
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{
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return SConfig::GetInstance().bCPUThread;
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}
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static void UpdateInterrupts_Wrapper(u64 userdata, s64 cyclesLate)
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{
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UpdateInterrupts(userdata);
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}
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void SCPFifoStruct::DoState(PointerWrap& p)
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{
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p.Do(CPBase);
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p.Do(CPEnd);
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p.Do(CPHiWatermark);
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p.Do(CPLoWatermark);
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p.Do(CPReadWriteDistance);
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p.Do(CPWritePointer);
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p.Do(CPReadPointer);
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p.Do(CPBreakpoint);
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p.Do(SafeCPReadPointer);
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p.Do(bFF_GPLinkEnable);
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p.Do(bFF_GPReadEnable);
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p.Do(bFF_BPEnable);
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p.Do(bFF_BPInt);
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p.Do(bFF_Breakpoint);
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p.Do(bFF_LoWatermarkInt);
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p.Do(bFF_HiWatermarkInt);
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p.Do(bFF_LoWatermark);
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p.Do(bFF_HiWatermark);
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}
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void DoState(PointerWrap& p)
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{
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p.DoPOD(m_CPStatusReg);
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p.DoPOD(m_CPCtrlReg);
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p.DoPOD(m_CPClearReg);
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p.Do(m_bboxleft);
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p.Do(m_bboxtop);
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p.Do(m_bboxright);
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p.Do(m_bboxbottom);
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p.Do(m_tokenReg);
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fifo.DoState(p);
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p.Do(s_interrupt_set);
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p.Do(s_interrupt_waiting);
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}
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static inline void WriteLow(volatile u32& _reg, u16 lowbits)
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{
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Common::AtomicStore(_reg, (_reg & 0xFFFF0000) | lowbits);
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}
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static inline void WriteHigh(volatile u32& _reg, u16 highbits)
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{
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Common::AtomicStore(_reg, (_reg & 0x0000FFFF) | ((u32)highbits << 16));
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}
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static inline u16 ReadLow(u32 _reg)
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{
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return (u16)(_reg & 0xFFFF);
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}
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static inline u16 ReadHigh(u32 _reg)
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{
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return (u16)(_reg >> 16);
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}
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void Init()
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{
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m_CPStatusReg.Hex = 0;
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m_CPStatusReg.CommandIdle = 1;
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m_CPStatusReg.ReadIdle = 1;
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m_CPCtrlReg.Hex = 0;
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m_CPClearReg.Hex = 0;
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m_bboxleft = 0;
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m_bboxtop = 0;
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m_bboxright = 640;
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m_bboxbottom = 480;
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m_tokenReg = 0;
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memset(&fifo, 0, sizeof(fifo));
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fifo.bFF_Breakpoint = 0;
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fifo.bFF_HiWatermark = 0;
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fifo.bFF_HiWatermarkInt = 0;
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fifo.bFF_LoWatermark = 0;
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fifo.bFF_LoWatermarkInt = 0;
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s_interrupt_set.Clear();
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s_interrupt_waiting.Clear();
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et_UpdateInterrupts = CoreTiming::RegisterEvent("CPInterrupt", UpdateInterrupts_Wrapper);
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}
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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constexpr u16 WMASK_NONE = 0x0000;
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constexpr u16 WMASK_ALL = 0xffff;
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constexpr u16 WMASK_LO_ALIGN_32BIT = 0xffe0;
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const u16 WMASK_HI_RESTRICT = SConfig::GetInstance().bWii ? 0x1fff : 0x03ff;
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struct
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{
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u32 addr;
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u16* ptr;
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bool readonly;
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// FIFO mmio regs in the range [cc000020-cc00003e] have certain bits that always read as 0
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// For _LO registers in this range, only bits 0xffe0 can be set
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// For _HI registers in this range, only bits 0x03ff can be set on GCN and 0x1fff on Wii
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u16 wmask;
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} directly_mapped_vars[] = {
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{FIFO_TOKEN_REGISTER, &m_tokenReg, false, WMASK_ALL},
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// Bounding box registers are read only.
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{FIFO_BOUNDING_BOX_LEFT, &m_bboxleft, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_RIGHT, &m_bboxright, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_TOP, &m_bboxtop, true, WMASK_NONE},
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{FIFO_BOUNDING_BOX_BOTTOM, &m_bboxbottom, true, WMASK_NONE},
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{FIFO_BASE_LO, MMIO::Utils::LowPart(&fifo.CPBase), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_BASE_HI, MMIO::Utils::HighPart(&fifo.CPBase), false, WMASK_HI_RESTRICT},
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{FIFO_END_LO, MMIO::Utils::LowPart(&fifo.CPEnd), false, WMASK_LO_ALIGN_32BIT},
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{FIFO_END_HI, MMIO::Utils::HighPart(&fifo.CPEnd), false, WMASK_HI_RESTRICT},
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{FIFO_HI_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPHiWatermark), false,
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WMASK_LO_ALIGN_32BIT},
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{FIFO_HI_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPHiWatermark), false, WMASK_HI_RESTRICT},
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{FIFO_LO_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPLoWatermark), false,
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WMASK_LO_ALIGN_32BIT},
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{FIFO_LO_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPLoWatermark), false, WMASK_HI_RESTRICT},
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// FIFO_RW_DISTANCE has some complex read code different for
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// single/dual core.
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{FIFO_WRITE_POINTER_LO, MMIO::Utils::LowPart(&fifo.CPWritePointer), false,
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WMASK_LO_ALIGN_32BIT},
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{FIFO_WRITE_POINTER_HI, MMIO::Utils::HighPart(&fifo.CPWritePointer), false,
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WMASK_HI_RESTRICT},
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// FIFO_READ_POINTER has different code for single/dual core.
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};
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for (auto& mapped_var : directly_mapped_vars)
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{
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mmio->Register(base | mapped_var.addr, MMIO::DirectRead<u16>(mapped_var.ptr),
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mapped_var.readonly ? MMIO::InvalidWrite<u16>() :
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MMIO::DirectWrite<u16>(mapped_var.ptr, mapped_var.wmask));
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}
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mmio->Register(base | FIFO_BP_LO, MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPBreakpoint)),
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MMIO::ComplexWrite<u16>([WMASK_LO_ALIGN_32BIT](u32, u16 val) {
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WriteLow(fifo.CPBreakpoint, val & WMASK_LO_ALIGN_32BIT);
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}));
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mmio->Register(base | FIFO_BP_HI,
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MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPBreakpoint)),
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MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
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WriteHigh(fifo.CPBreakpoint, val & WMASK_HI_RESTRICT);
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}));
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// Timing and metrics MMIOs are stubbed with fixed values.
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struct
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{
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u32 addr;
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u16 value;
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} metrics_mmios[] = {
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{XF_RASBUSY_L, 0},
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{XF_RASBUSY_H, 0},
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{XF_CLKS_L, 0},
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{XF_CLKS_H, 0},
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{XF_WAIT_IN_L, 0},
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{XF_WAIT_IN_H, 0},
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{XF_WAIT_OUT_L, 0},
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{XF_WAIT_OUT_H, 0},
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{VCACHE_METRIC_CHECK_L, 0},
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{VCACHE_METRIC_CHECK_H, 0},
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{VCACHE_METRIC_MISS_L, 0},
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{VCACHE_METRIC_MISS_H, 0},
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{VCACHE_METRIC_STALL_L, 0},
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{VCACHE_METRIC_STALL_H, 0},
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{CLKS_PER_VTX_OUT, 4},
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};
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for (auto& metrics_mmio : metrics_mmios)
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{
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mmio->Register(base | metrics_mmio.addr, MMIO::Constant<u16>(metrics_mmio.value),
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MMIO::InvalidWrite<u16>());
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}
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mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](u32) {
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SetCpStatusRegister();
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return m_CPStatusReg.Hex;
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}),
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MMIO::InvalidWrite<u16>());
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mmio->Register(base | CTRL_REGISTER, MMIO::DirectRead<u16>(&m_CPCtrlReg.Hex),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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UCPCtrlReg tmp(val);
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m_CPCtrlReg.Hex = tmp.Hex;
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SetCpControlRegister();
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Fifo::RunGpu();
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}));
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mmio->Register(base | CLEAR_REGISTER, MMIO::DirectRead<u16>(&m_CPClearReg.Hex),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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UCPClearReg tmp(val);
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m_CPClearReg.Hex = tmp.Hex;
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SetCpClearRegister();
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Fifo::RunGpu();
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}));
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mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());
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// Some MMIOs have different handlers for single core vs. dual core mode.
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mmio->Register(base | FIFO_RW_DISTANCE_LO,
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IsOnThread() ?
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MMIO::ComplexRead<u16>([](u32) {
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if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
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return ReadLow(fifo.CPWritePointer - fifo.SafeCPReadPointer);
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else
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return ReadLow(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
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fifo.CPBase + 32);
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}) :
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MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)),
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MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
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WMASK_LO_ALIGN_32BIT));
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mmio->Register(base | FIFO_RW_DISTANCE_HI,
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IsOnThread() ?
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MMIO::ComplexRead<u16>([](u32) {
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if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
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return ReadHigh(fifo.CPWritePointer - fifo.SafeCPReadPointer);
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else
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return ReadHigh(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
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fifo.CPBase + 32);
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}) :
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MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadWriteDistance)),
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MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
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WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
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Fifo::SyncGPU(Fifo::SyncGPUReason::Other);
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Fifo::RunGpu();
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}));
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mmio->Register(
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base | FIFO_READ_POINTER_LO,
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IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
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MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
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MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
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mmio->Register(
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base | FIFO_READ_POINTER_HI,
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IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.SafeCPReadPointer)) :
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MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer)),
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IsOnThread() ?
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MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
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WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
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fifo.SafeCPReadPointer = fifo.CPReadPointer;
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}) :
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MMIO::DirectWrite<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer), WMASK_HI_RESTRICT));
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}
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void GatherPipeBursted()
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{
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SetCPStatusFromCPU();
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// if we aren't linked, we don't care about gather pipe data
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if (!m_CPCtrlReg.GPLinkEnable)
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{
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if (IsOnThread() && !Fifo::UseDeterministicGPUThread())
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{
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// In multibuffer mode is not allowed write in the same FIFO attached to the GPU.
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// Fix Pokemon XD in DC mode.
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if ((ProcessorInterface::Fifo_CPUEnd == fifo.CPEnd) &&
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(ProcessorInterface::Fifo_CPUBase == fifo.CPBase) && fifo.CPReadWriteDistance > 0)
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{
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Fifo::FlushGpu();
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}
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}
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Fifo::RunGpu();
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return;
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}
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// update the fifo pointer
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if (fifo.CPWritePointer == fifo.CPEnd)
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fifo.CPWritePointer = fifo.CPBase;
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else
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fifo.CPWritePointer += GATHER_PIPE_SIZE;
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if (m_CPCtrlReg.GPReadEnable && m_CPCtrlReg.GPLinkEnable)
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{
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ProcessorInterface::Fifo_CPUWritePointer = fifo.CPWritePointer;
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ProcessorInterface::Fifo_CPUBase = fifo.CPBase;
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ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd;
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}
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// If the game is running close to overflowing, make the exception checking more frequent.
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if (fifo.bFF_HiWatermark)
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CoreTiming::ForceExceptionCheck(0);
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Common::AtomicAdd(fifo.CPReadWriteDistance, GATHER_PIPE_SIZE);
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Fifo::RunGpu();
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ASSERT_MSG(COMMANDPROCESSOR, fifo.CPReadWriteDistance <= fifo.CPEnd - fifo.CPBase,
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"FIFO is overflowed by GatherPipe !\nCPU thread is too fast!");
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// check if we are in sync
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ASSERT_MSG(COMMANDPROCESSOR, fifo.CPWritePointer == ProcessorInterface::Fifo_CPUWritePointer,
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"FIFOs linked but out of sync");
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ASSERT_MSG(COMMANDPROCESSOR, fifo.CPBase == ProcessorInterface::Fifo_CPUBase,
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"FIFOs linked but out of sync");
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ASSERT_MSG(COMMANDPROCESSOR, fifo.CPEnd == ProcessorInterface::Fifo_CPUEnd,
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"FIFOs linked but out of sync");
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}
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void UpdateInterrupts(u64 userdata)
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{
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if (userdata)
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{
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s_interrupt_set.Set();
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DEBUG_LOG(COMMANDPROCESSOR, "Interrupt set");
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ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true);
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}
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else
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{
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s_interrupt_set.Clear();
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DEBUG_LOG(COMMANDPROCESSOR, "Interrupt cleared");
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ProcessorInterface::SetInterrupt(INT_CAUSE_CP, false);
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}
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CoreTiming::ForceExceptionCheck(0);
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s_interrupt_waiting.Clear();
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Fifo::RunGpu();
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}
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void UpdateInterruptsFromVideoBackend(u64 userdata)
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{
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if (!Fifo::UseDeterministicGPUThread())
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CoreTiming::ScheduleEvent(0, et_UpdateInterrupts, userdata, CoreTiming::FromThread::NON_CPU);
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}
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bool IsInterruptWaiting()
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{
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return s_interrupt_waiting.IsSet();
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}
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void SetCPStatusFromGPU()
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{
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// breakpoint
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if (fifo.bFF_BPEnable)
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{
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if (fifo.CPBreakpoint == fifo.CPReadPointer)
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{
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if (!fifo.bFF_Breakpoint)
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{
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DEBUG_LOG(COMMANDPROCESSOR, "Hit breakpoint at %i", fifo.CPReadPointer);
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fifo.bFF_Breakpoint = true;
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}
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}
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else
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{
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if (fifo.bFF_Breakpoint)
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DEBUG_LOG(COMMANDPROCESSOR, "Cleared breakpoint at %i", fifo.CPReadPointer);
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fifo.bFF_Breakpoint = false;
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}
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}
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else
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{
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if (fifo.bFF_Breakpoint)
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DEBUG_LOG(COMMANDPROCESSOR, "Cleared breakpoint at %i", fifo.CPReadPointer);
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fifo.bFF_Breakpoint = false;
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}
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// overflow & underflow check
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fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
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fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
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bool bpInt = fifo.bFF_Breakpoint && fifo.bFF_BPInt;
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bool ovfInt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt;
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bool undfInt = fifo.bFF_LoWatermark && fifo.bFF_LoWatermarkInt;
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bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
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if (interrupt != s_interrupt_set.IsSet() && !s_interrupt_waiting.IsSet())
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{
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u64 userdata = interrupt ? 1 : 0;
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if (IsOnThread())
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{
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if (!interrupt || bpInt || undfInt || ovfInt)
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{
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// Schedule the interrupt asynchronously
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s_interrupt_waiting.Set();
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CommandProcessor::UpdateInterruptsFromVideoBackend(userdata);
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}
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}
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else
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{
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CommandProcessor::UpdateInterrupts(userdata);
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}
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}
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}
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void SetCPStatusFromCPU()
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{
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// overflow & underflow check
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fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
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fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
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bool bpInt = fifo.bFF_Breakpoint && fifo.bFF_BPInt;
|
|
bool ovfInt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt;
|
|
bool undfInt = fifo.bFF_LoWatermark && fifo.bFF_LoWatermarkInt;
|
|
|
|
bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
|
|
|
|
if (interrupt != s_interrupt_set.IsSet() && !s_interrupt_waiting.IsSet())
|
|
{
|
|
u64 userdata = interrupt ? 1 : 0;
|
|
if (IsOnThread())
|
|
{
|
|
if (!interrupt || bpInt || undfInt || ovfInt)
|
|
{
|
|
s_interrupt_set.Set(interrupt);
|
|
DEBUG_LOG(COMMANDPROCESSOR, "Interrupt set");
|
|
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, interrupt);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
CommandProcessor::UpdateInterrupts(userdata);
|
|
}
|
|
}
|
|
}
|
|
|
|
void SetCpStatusRegister()
|
|
{
|
|
// Here always there is one fifo attached to the GPU
|
|
m_CPStatusReg.Breakpoint = fifo.bFF_Breakpoint;
|
|
m_CPStatusReg.ReadIdle = !fifo.CPReadWriteDistance || (fifo.CPReadPointer == fifo.CPWritePointer);
|
|
m_CPStatusReg.CommandIdle =
|
|
!fifo.CPReadWriteDistance || Fifo::AtBreakpoint() || !fifo.bFF_GPReadEnable;
|
|
m_CPStatusReg.UnderflowLoWatermark = fifo.bFF_LoWatermark;
|
|
m_CPStatusReg.OverflowHiWatermark = fifo.bFF_HiWatermark;
|
|
|
|
DEBUG_LOG(COMMANDPROCESSOR, "\t Read from STATUS_REGISTER : %04x", m_CPStatusReg.Hex);
|
|
DEBUG_LOG(
|
|
COMMANDPROCESSOR, "(r) status: iBP %s | fReadIdle %s | fCmdIdle %s | iOvF %s | iUndF %s",
|
|
m_CPStatusReg.Breakpoint ? "ON" : "OFF", m_CPStatusReg.ReadIdle ? "ON" : "OFF",
|
|
m_CPStatusReg.CommandIdle ? "ON" : "OFF", m_CPStatusReg.OverflowHiWatermark ? "ON" : "OFF",
|
|
m_CPStatusReg.UnderflowLoWatermark ? "ON" : "OFF");
|
|
}
|
|
|
|
void SetCpControlRegister()
|
|
{
|
|
fifo.bFF_BPInt = m_CPCtrlReg.BPInt;
|
|
fifo.bFF_BPEnable = m_CPCtrlReg.BPEnable;
|
|
fifo.bFF_HiWatermarkInt = m_CPCtrlReg.FifoOverflowIntEnable;
|
|
fifo.bFF_LoWatermarkInt = m_CPCtrlReg.FifoUnderflowIntEnable;
|
|
fifo.bFF_GPLinkEnable = m_CPCtrlReg.GPLinkEnable;
|
|
|
|
if (fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable)
|
|
{
|
|
fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
|
|
Fifo::FlushGpu();
|
|
}
|
|
else
|
|
{
|
|
fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
|
|
}
|
|
|
|
DEBUG_LOG(COMMANDPROCESSOR, "\t GPREAD %s | BP %s | Int %s | OvF %s | UndF %s | LINK %s",
|
|
fifo.bFF_GPReadEnable ? "ON" : "OFF", fifo.bFF_BPEnable ? "ON" : "OFF",
|
|
fifo.bFF_BPInt ? "ON" : "OFF", m_CPCtrlReg.FifoOverflowIntEnable ? "ON" : "OFF",
|
|
m_CPCtrlReg.FifoUnderflowIntEnable ? "ON" : "OFF",
|
|
m_CPCtrlReg.GPLinkEnable ? "ON" : "OFF");
|
|
}
|
|
|
|
// NOTE: We intentionally don't emulate this function at the moment.
|
|
// We don't emulate proper GP timing anyway at the moment, so it would just slow down emulation.
|
|
void SetCpClearRegister()
|
|
{
|
|
}
|
|
|
|
void HandleUnknownOpcode(u8 cmd_byte, void* buffer, bool preprocess)
|
|
{
|
|
// TODO(Omega): Maybe dump FIFO to file on this error
|
|
PanicAlertT("GFX FIFO: Unknown Opcode (0x%02x @ %p, %s).\n"
|
|
"This means one of the following:\n"
|
|
"* The emulated GPU got desynced, disabling dual core can help\n"
|
|
"* Command stream corrupted by some spurious memory bug\n"
|
|
"* This really is an unknown opcode (unlikely)\n"
|
|
"* Some other sort of bug\n\n"
|
|
"Further errors will be sent to the Video Backend log and\n"
|
|
"Dolphin will now likely crash or hang. Enjoy.",
|
|
cmd_byte, buffer, preprocess ? "preprocess=true" : "preprocess=false");
|
|
|
|
{
|
|
PanicAlert("Illegal command %02x\n"
|
|
"CPBase: 0x%08x\n"
|
|
"CPEnd: 0x%08x\n"
|
|
"CPHiWatermark: 0x%08x\n"
|
|
"CPLoWatermark: 0x%08x\n"
|
|
"CPReadWriteDistance: 0x%08x\n"
|
|
"CPWritePointer: 0x%08x\n"
|
|
"CPReadPointer: 0x%08x\n"
|
|
"CPBreakpoint: 0x%08x\n"
|
|
"bFF_GPReadEnable: %s\n"
|
|
"bFF_BPEnable: %s\n"
|
|
"bFF_BPInt: %s\n"
|
|
"bFF_Breakpoint: %s\n"
|
|
"bFF_GPLinkEnable: %s\n"
|
|
"bFF_HiWatermarkInt: %s\n"
|
|
"bFF_LoWatermarkInt: %s\n",
|
|
cmd_byte, fifo.CPBase, fifo.CPEnd, fifo.CPHiWatermark, fifo.CPLoWatermark,
|
|
fifo.CPReadWriteDistance, fifo.CPWritePointer, fifo.CPReadPointer, fifo.CPBreakpoint,
|
|
fifo.bFF_GPReadEnable ? "true" : "false", fifo.bFF_BPEnable ? "true" : "false",
|
|
fifo.bFF_BPInt ? "true" : "false", fifo.bFF_Breakpoint ? "true" : "false",
|
|
fifo.bFF_GPLinkEnable ? "true" : "false", fifo.bFF_HiWatermarkInt ? "true" : "false",
|
|
fifo.bFF_LoWatermarkInt ? "true" : "false");
|
|
}
|
|
}
|
|
|
|
} // end of namespace CommandProcessor
|