mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-15 22:09:19 -07:00
a811370329
In particular this fixes the 6666 colour format We were loading from the wrong location and it was causing /terrible/ colour changes. This also fixes a bug in the all the colour formats(except 888) where the unaligned path was loading in to the wrong register.
571 lines
18 KiB
C++
571 lines
18 KiB
C++
// Copyright 2015 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include "VideoCommon/VertexLoaderARM64.h"
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#include "VideoCommon/VertexLoaderManager.h"
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using namespace Arm64Gen;
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ARM64Reg src_reg = X0;
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ARM64Reg dst_reg = X1;
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ARM64Reg count_reg = W2;
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ARM64Reg skipped_reg = W17;
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ARM64Reg scratch1_reg = W16;
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ARM64Reg scratch2_reg = W15;
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ARM64Reg scratch3_reg = W14;
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ARM64Reg scratch4_reg = W13;
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ARM64Reg saved_count = W12;
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ARM64Reg stride_reg = X11;
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ARM64Reg arraybase_reg = X10;
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ARM64Reg scale_reg = X9;
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static const float GC_ALIGNED16(scale_factors[]) =
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{
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1.0 / (1ULL << 0), 1.0 / (1ULL << 1), 1.0 / (1ULL << 2), 1.0 / (1ULL << 3),
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1.0 / (1ULL << 4), 1.0 / (1ULL << 5), 1.0 / (1ULL << 6), 1.0 / (1ULL << 7),
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1.0 / (1ULL << 8), 1.0 / (1ULL << 9), 1.0 / (1ULL << 10), 1.0 / (1ULL << 11),
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1.0 / (1ULL << 12), 1.0 / (1ULL << 13), 1.0 / (1ULL << 14), 1.0 / (1ULL << 15),
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1.0 / (1ULL << 16), 1.0 / (1ULL << 17), 1.0 / (1ULL << 18), 1.0 / (1ULL << 19),
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1.0 / (1ULL << 20), 1.0 / (1ULL << 21), 1.0 / (1ULL << 22), 1.0 / (1ULL << 23),
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1.0 / (1ULL << 24), 1.0 / (1ULL << 25), 1.0 / (1ULL << 26), 1.0 / (1ULL << 27),
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1.0 / (1ULL << 28), 1.0 / (1ULL << 29), 1.0 / (1ULL << 30), 1.0 / (1ULL << 31),
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};
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VertexLoaderARM64::VertexLoaderARM64(const TVtxDesc& vtx_desc, const VAT& vtx_att)
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: VertexLoaderBase(vtx_desc, vtx_att), m_float_emit(this)
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{
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if (!IsInitialized())
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return;
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AllocCodeSpace(4096);
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ClearCodeSpace();
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GenerateVertexLoader();
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WriteProtect();
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}
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void VertexLoaderARM64::GetVertexAddr(int array, u64 attribute, ARM64Reg reg)
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{
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ADD(reg, src_reg, m_src_ofs);
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if (attribute & MASK_INDEXED)
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{
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if (attribute == INDEX8)
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{
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LDRB(INDEX_UNSIGNED, scratch1_reg, reg, 0);
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m_src_ofs += 1;
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}
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else
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{
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LDRH(INDEX_UNSIGNED, scratch1_reg, reg, 0);
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m_src_ofs += 2;
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REV16(scratch1_reg, scratch1_reg);
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}
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if (array == ARRAY_POSITION)
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{
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EOR(scratch2_reg, scratch1_reg, 0, attribute == INDEX8 ? 7 : 15); // 0xFF : 0xFFFF
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m_skip_vertex = CBZ(scratch2_reg);
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}
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LDR(INDEX_UNSIGNED, scratch2_reg, stride_reg, array * 4);
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MUL(scratch1_reg, scratch1_reg, scratch2_reg);
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LDR(INDEX_UNSIGNED, EncodeRegTo64(scratch2_reg), arraybase_reg, array * 8);
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ADD(EncodeRegTo64(reg), EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch2_reg));
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}
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}
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s32 VertexLoaderARM64::GetAddressImm(int array, u64 attribute, Arm64Gen::ARM64Reg reg, u32 align)
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{
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if (attribute & MASK_INDEXED ||
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(m_src_ofs > 255 && (m_src_ofs & (align - 1))))
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GetVertexAddr(array, attribute, reg);
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else
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return m_src_ofs;
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return -1;
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}
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int VertexLoaderARM64::ReadVertex(u64 attribute, int format, int count_in, int count_out, bool dequantize, u8 scaling_exponent, AttributeFormat* native_format, s32 offset)
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{
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ARM64Reg coords = count_in == 3 ? Q31 : D31;
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ARM64Reg scale = count_in == 3 ? Q30 : D30;
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int elem_size = 1 << (format / 2);
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int load_bytes = elem_size * count_in;
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int load_size = load_bytes == 1 ? 1 : load_bytes <= 2 ? 2 : load_bytes <= 4 ? 4 : load_bytes <= 8 ? 8 : 16;
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load_size <<= 3;
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elem_size <<= 3;
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if (offset == -1)
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{
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if (count_in == 1)
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m_float_emit.LDR(elem_size, INDEX_UNSIGNED, coords, EncodeRegTo64(scratch1_reg), 0);
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else
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m_float_emit.LD1(elem_size, 1, coords, EncodeRegTo64(scratch1_reg));
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}
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else if (offset & (load_size - 1)) // Not aligned - unscaled
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{
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m_float_emit.LDUR(load_size, coords, src_reg, offset);
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}
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else
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{
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m_float_emit.LDR(load_size, INDEX_UNSIGNED, coords, src_reg, offset);
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}
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if (format != FORMAT_FLOAT)
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{
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// Extend and convert to float
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switch (format)
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{
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case FORMAT_UBYTE:
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m_float_emit.UXTL(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.UXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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case FORMAT_BYTE:
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m_float_emit.SXTL(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.SXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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case FORMAT_USHORT:
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m_float_emit.REV16(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.UXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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case FORMAT_SHORT:
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m_float_emit.REV16(8, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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m_float_emit.SXTL(16, EncodeRegToDouble(coords), EncodeRegToDouble(coords));
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break;
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}
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m_float_emit.SCVTF(32, coords, coords);
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if (dequantize && scaling_exponent)
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{
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m_float_emit.LDR(32, INDEX_UNSIGNED, scale, scale_reg, scaling_exponent * 4);
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m_float_emit.FMUL(32, coords, coords, scale, 0);
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}
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}
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else
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{
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m_float_emit.REV32(8, coords, coords);
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}
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const u32 write_size = count_out == 3 ? 128 : count_out * 32;
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const u32 mask = count_out == 3 ? 0xF : count_out == 2 ? 0x7 : 0x3;
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if (m_dst_ofs < 256)
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{
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m_float_emit.STUR(write_size, coords, dst_reg, m_dst_ofs);
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}
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else if (!(m_dst_ofs & mask))
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{
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m_float_emit.STR(write_size, INDEX_UNSIGNED, coords, dst_reg, m_dst_ofs);
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}
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else
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{
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ADD(EncodeRegTo64(scratch2_reg), dst_reg, m_dst_ofs);
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m_float_emit.ST1(32, 1, coords, EncodeRegTo64(scratch2_reg));
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}
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// Z-Freeze
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if (native_format == &m_native_vtx_decl.position)
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{
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CMP(count_reg, 3);
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FixupBranch dont_store = B(CC_GT);
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MOVI2R(EncodeRegTo64(scratch2_reg), (u64)VertexLoaderManager::position_cache);
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ORR(scratch1_reg, WSP, count_reg, ArithOption(count_reg, ST_LSL, 4));
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ADD(EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch2_reg));
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m_float_emit.STUR(write_size, coords, EncodeRegTo64(scratch1_reg), -16);
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SetJumpTarget(dont_store);
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}
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native_format->components = count_out;
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native_format->enable = true;
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native_format->offset = m_dst_ofs;
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native_format->type = VAR_FLOAT;
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native_format->integer = false;
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m_dst_ofs += sizeof(float) * count_out;
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if (attribute == DIRECT)
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m_src_ofs += load_bytes;
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return load_bytes;
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}
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void VertexLoaderARM64::ReadColor(u64 attribute, int format, s32 offset)
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{
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int load_bytes = 0;
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switch (format)
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{
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case FORMAT_24B_888:
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case FORMAT_32B_888x:
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case FORMAT_32B_8888:
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if (offset == -1)
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LDR(INDEX_UNSIGNED, scratch2_reg, EncodeRegTo64(scratch1_reg), 0);
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else if (offset & 3) // Not aligned - unscaled
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LDUR(scratch2_reg, src_reg, offset);
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else
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LDR(INDEX_UNSIGNED, scratch2_reg, src_reg, offset);
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if (format != FORMAT_32B_8888)
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ORR(scratch2_reg, scratch2_reg, 8, 7); // 0xFF000000
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STR(INDEX_UNSIGNED, scratch2_reg, dst_reg, m_dst_ofs);
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load_bytes = 3 + (format != FORMAT_24B_888);
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break;
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case FORMAT_16B_565:
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// RRRRRGGG GGGBBBBB
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// AAAAAAAA BBBBBBBB GGGGGGGG RRRRRRRR
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if (offset == -1)
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LDRH(INDEX_UNSIGNED, scratch3_reg, EncodeRegTo64(scratch1_reg), 0);
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else if (offset & 1) // Not aligned - unscaled
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LDURH(scratch3_reg, src_reg, offset);
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else
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LDRH(INDEX_UNSIGNED, scratch3_reg, src_reg, offset);
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REV16(scratch3_reg, scratch3_reg);
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// B
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AND(scratch2_reg, scratch3_reg, 32, 4);
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ORR(scratch2_reg, WSP, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 3));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSR, 5));
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ORR(scratch1_reg, WSP, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 16));
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// G
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UBFM(scratch2_reg, scratch3_reg, 5, 10);
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ORR(scratch2_reg, WSP, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSR, 6));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 8));
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// R
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UBFM(scratch2_reg, scratch3_reg, 11, 15);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 3));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSR, 2));
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// A
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ORR(scratch2_reg, scratch2_reg, 8, 7); // 0xFF000000
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STR(INDEX_UNSIGNED, scratch1_reg, dst_reg, m_dst_ofs);
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load_bytes = 2;
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break;
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case FORMAT_16B_4444:
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// BBBBAAAA RRRRGGGG
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// REV16 - RRRRGGGG BBBBAAAA
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// AAAAAAAA BBBBBBBB GGGGGGGG RRRRRRRR
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if (offset == -1)
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LDRH(INDEX_UNSIGNED, scratch3_reg, EncodeRegTo64(scratch1_reg), 0);
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else if (offset & 1) // Not aligned - unscaled
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LDURH(scratch3_reg, src_reg, offset);
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else
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LDRH(INDEX_UNSIGNED, scratch3_reg, src_reg, offset);
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// R
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UBFM(scratch1_reg, scratch3_reg, 4, 7);
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// G
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AND(scratch2_reg, scratch3_reg, 32, 3);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 8));
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// B
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UBFM(scratch2_reg, scratch3_reg, 12, 15);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 16));
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// A
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UBFM(scratch2_reg, scratch3_reg, 8, 11);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 24));
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// Final duplication
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ORR(scratch1_reg, scratch1_reg, scratch1_reg, ArithOption(scratch1_reg, ST_LSL, 4));
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STR(INDEX_UNSIGNED, scratch1_reg, dst_reg, m_dst_ofs);
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load_bytes = 2;
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break;
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case FORMAT_24B_6666:
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// RRRRRRGG GGGGBBBB BBAAAAAA
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// AAAAAAAA BBBBBBBB GGGGGGGG RRRRRRRR
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if (offset == -1)
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{
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LDUR(scratch3_reg, EncodeRegTo64(scratch1_reg), -1);
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}
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else
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{
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offset -= 1;
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if (offset & 3) // Not aligned - unscaled
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LDUR(scratch3_reg, src_reg, offset);
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else
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LDR(INDEX_UNSIGNED, scratch3_reg, src_reg, offset);
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}
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REV32(scratch3_reg, scratch3_reg);
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// A
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UBFM(scratch2_reg, scratch3_reg, 0, 5);
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ORR(scratch2_reg, WSP, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSR, 6));
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ORR(scratch1_reg, WSP, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 24));
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// B
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UBFM(scratch2_reg, scratch3_reg, 6, 11);
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ORR(scratch2_reg, WSP, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSR, 6));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 16));
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// G
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UBFM(scratch2_reg, scratch3_reg, 12, 17);
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ORR(scratch2_reg, WSP, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 2));
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ORR(scratch2_reg, scratch2_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSR, 6));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 8));
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// R
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UBFM(scratch2_reg, scratch3_reg, 18, 23);
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSL, 2));
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ORR(scratch1_reg, scratch1_reg, scratch2_reg, ArithOption(scratch2_reg, ST_LSR, 4));
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STR(INDEX_UNSIGNED, scratch1_reg, dst_reg, m_dst_ofs);
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load_bytes = 3;
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break;
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}
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if (attribute == DIRECT)
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m_src_ofs += load_bytes;
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}
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void VertexLoaderARM64::GenerateVertexLoader()
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{
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// R0 - Source pointer
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// R1 - Destination pointer
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// R2 - Count
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// R30 - LR
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//
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// R0 return how many
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//
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// Registers we don't have to worry about saving
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// R9-R17 are caller saved temporaries
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// R18 is a temporary or platform specific register(iOS)
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//
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// VFP registers
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// We can touch all except v8-v15
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// If we need to use those, we need to retain the lower 64bits(!) of the register
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MOV(skipped_reg, WSP);
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MOV(saved_count, count_reg);
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MOVI2R(stride_reg, (u64)&g_main_cp_state.array_strides);
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MOVI2R(arraybase_reg, (u64)&VertexLoaderManager::cached_arraybases);
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MOVI2R(scale_reg, (u64)&scale_factors);
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const u8* loop_start = GetCodePtr();
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if (m_VtxDesc.PosMatIdx)
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{
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LDRB(INDEX_UNSIGNED, scratch1_reg, src_reg, m_src_ofs);
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AND(scratch1_reg, scratch1_reg, 0, 5);
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STR(INDEX_UNSIGNED, scratch1_reg, dst_reg, m_dst_ofs);
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// Z-Freeze
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CMP(count_reg, 3);
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FixupBranch dont_store = B(CC_GT);
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MOVI2R(EncodeRegTo64(scratch2_reg), (u64)VertexLoaderManager::position_matrix_index - sizeof(u32));
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STR(INDEX_UNSIGNED, scratch1_reg, EncodeRegTo64(scratch2_reg), 0);
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SetJumpTarget(dont_store);
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m_native_components |= VB_HAS_POSMTXIDX;
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m_native_vtx_decl.posmtx.components = 4;
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m_native_vtx_decl.posmtx.enable = true;
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m_native_vtx_decl.posmtx.offset = m_dst_ofs;
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m_native_vtx_decl.posmtx.type = VAR_UNSIGNED_BYTE;
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m_native_vtx_decl.posmtx.integer = true;
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m_src_ofs += sizeof(u8);
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m_dst_ofs += sizeof(u32);
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}
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u32 texmatidx_ofs[8];
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const u64 tm[8] = {
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m_VtxDesc.Tex0MatIdx, m_VtxDesc.Tex1MatIdx, m_VtxDesc.Tex2MatIdx, m_VtxDesc.Tex3MatIdx,
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m_VtxDesc.Tex4MatIdx, m_VtxDesc.Tex5MatIdx, m_VtxDesc.Tex6MatIdx, m_VtxDesc.Tex7MatIdx,
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};
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for (int i = 0; i < 8; i++)
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{
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if (tm[i])
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texmatidx_ofs[i] = m_src_ofs++;
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}
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// Position
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{
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int elem_size = 1 << (m_VtxAttr.PosFormat / 2);
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int load_bytes = elem_size * (m_VtxAttr.PosElements + 2);
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int load_size = load_bytes == 1 ? 1 : load_bytes <= 2 ? 2 : load_bytes <= 4 ? 4 : load_bytes <= 8 ? 8 : 16;
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load_size <<= 3;
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s32 offset = GetAddressImm(ARRAY_POSITION, m_VtxDesc.Position, EncodeRegTo64(scratch1_reg), load_size);
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int pos_elements = m_VtxAttr.PosElements + 2;
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ReadVertex(m_VtxDesc.Position, m_VtxAttr.PosFormat, pos_elements, pos_elements,
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m_VtxAttr.ByteDequant, m_VtxAttr.PosFrac, &m_native_vtx_decl.position, offset);
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}
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if (m_VtxDesc.Normal)
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{
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static const u8 map[8] = {7, 6, 15, 14};
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u8 scaling_exponent = map[m_VtxAttr.NormalFormat];
|
|
|
|
s32 offset = -1;
|
|
for (int i = 0; i < (m_VtxAttr.NormalElements ? 3 : 1); i++)
|
|
{
|
|
if (!i || m_VtxAttr.NormalIndex3)
|
|
{
|
|
int elem_size = 1 << (m_VtxAttr.NormalFormat / 2);
|
|
|
|
int load_bytes = elem_size * 3;
|
|
int load_size = load_bytes == 1 ? 1 : load_bytes <= 2 ? 2 : load_bytes <= 4 ? 4 : load_bytes <= 8 ? 8 : 16;
|
|
|
|
offset = GetAddressImm(ARRAY_NORMAL, m_VtxDesc.Normal, EncodeRegTo64(scratch1_reg), load_size << 3);
|
|
|
|
if (offset == -1)
|
|
ADD(EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch1_reg), i * elem_size * 3);
|
|
else
|
|
offset += i * elem_size * 3;
|
|
}
|
|
int bytes_read = ReadVertex(m_VtxDesc.Normal, m_VtxAttr.NormalFormat, 3, 3,
|
|
true, scaling_exponent, &m_native_vtx_decl.normals[i], offset);
|
|
|
|
if (offset == -1)
|
|
ADD(EncodeRegTo64(scratch1_reg), EncodeRegTo64(scratch1_reg), bytes_read);
|
|
else
|
|
offset += bytes_read;
|
|
}
|
|
|
|
m_native_components |= VB_HAS_NRM0;
|
|
if (m_VtxAttr.NormalElements)
|
|
m_native_components |= VB_HAS_NRM1 | VB_HAS_NRM2;
|
|
}
|
|
|
|
const u64 col[2] = {m_VtxDesc.Color0, m_VtxDesc.Color1};
|
|
for (int i = 0; i < 2; i++)
|
|
{
|
|
m_native_vtx_decl.colors[i].components = 4;
|
|
m_native_vtx_decl.colors[i].type = VAR_UNSIGNED_BYTE;
|
|
m_native_vtx_decl.colors[i].integer = false;
|
|
|
|
if (col[i])
|
|
{
|
|
u32 align = 4;
|
|
if (m_VtxAttr.color[i].Comp == FORMAT_16B_565 ||
|
|
m_VtxAttr.color[i].Comp == FORMAT_16B_4444)
|
|
align = 2;
|
|
|
|
s32 offset = GetAddressImm(ARRAY_COLOR + i, col[i], EncodeRegTo64(scratch1_reg), align);
|
|
ReadColor(col[i], m_VtxAttr.color[i].Comp, offset);
|
|
m_native_components |= VB_HAS_COL0 << i;
|
|
m_native_vtx_decl.colors[i].components = 4;
|
|
m_native_vtx_decl.colors[i].enable = true;
|
|
m_native_vtx_decl.colors[i].offset = m_dst_ofs;
|
|
m_native_vtx_decl.colors[i].type = VAR_UNSIGNED_BYTE;
|
|
m_native_vtx_decl.colors[i].integer = false;
|
|
m_dst_ofs += 4;
|
|
}
|
|
}
|
|
|
|
const u64 tc[8] = {
|
|
m_VtxDesc.Tex0Coord, m_VtxDesc.Tex1Coord, m_VtxDesc.Tex2Coord, m_VtxDesc.Tex3Coord,
|
|
m_VtxDesc.Tex4Coord, m_VtxDesc.Tex5Coord, m_VtxDesc.Tex6Coord, m_VtxDesc.Tex7Coord,
|
|
};
|
|
|
|
for (int i = 0; i < 8; i++)
|
|
{
|
|
m_native_vtx_decl.texcoords[i].offset = m_dst_ofs;
|
|
m_native_vtx_decl.texcoords[i].type = VAR_FLOAT;
|
|
m_native_vtx_decl.texcoords[i].integer = false;
|
|
|
|
int elements = m_VtxAttr.texCoord[i].Elements + 1;
|
|
if (tc[i])
|
|
{
|
|
m_native_components |= VB_HAS_UV0 << i;
|
|
|
|
int elem_size = 1 << (m_VtxAttr.texCoord[i].Format / 2);
|
|
int load_bytes = elem_size * (elements + 2);
|
|
int load_size = load_bytes == 1 ? 1 : load_bytes <= 2 ? 2 : load_bytes <= 4 ? 4 : load_bytes <= 8 ? 8 : 16;
|
|
load_size <<= 3;
|
|
|
|
s32 offset = GetAddressImm(ARRAY_TEXCOORD0 + i, tc[i], EncodeRegTo64(scratch1_reg), load_size);
|
|
u8 scaling_exponent = m_VtxAttr.texCoord[i].Frac;
|
|
ReadVertex(tc[i], m_VtxAttr.texCoord[i].Format, elements, tm[i] ? 2 : elements,
|
|
m_VtxAttr.ByteDequant, scaling_exponent, &m_native_vtx_decl.texcoords[i], offset);
|
|
}
|
|
if (tm[i])
|
|
{
|
|
m_native_components |= VB_HAS_TEXMTXIDX0 << i;
|
|
m_native_vtx_decl.texcoords[i].components = 3;
|
|
m_native_vtx_decl.texcoords[i].enable = true;
|
|
m_native_vtx_decl.texcoords[i].type = VAR_FLOAT;
|
|
m_native_vtx_decl.texcoords[i].integer = false;
|
|
|
|
LDRB(INDEX_UNSIGNED, scratch2_reg, src_reg, texmatidx_ofs[i]);
|
|
m_float_emit.UCVTF(S31, scratch2_reg);
|
|
|
|
if (tc[i])
|
|
{
|
|
m_float_emit.STR(32, INDEX_UNSIGNED, D31, dst_reg, m_dst_ofs);
|
|
m_dst_ofs += sizeof(float);
|
|
}
|
|
else
|
|
{
|
|
m_native_vtx_decl.texcoords[i].offset = m_dst_ofs;
|
|
|
|
if (m_dst_ofs < 256)
|
|
{
|
|
STUR(SP, dst_reg, m_dst_ofs);
|
|
}
|
|
else if (!(m_dst_ofs & 7))
|
|
{
|
|
// If m_dst_ofs isn't 8byte aligned we can't store an 8byte zero register
|
|
// So store two 4byte zero registers
|
|
// The destination is always 4byte aligned
|
|
STR(INDEX_UNSIGNED, WSP, dst_reg, m_dst_ofs);
|
|
STR(INDEX_UNSIGNED, WSP, dst_reg, m_dst_ofs + 4);
|
|
}
|
|
else
|
|
{
|
|
STR(INDEX_UNSIGNED, SP, dst_reg, m_dst_ofs);
|
|
}
|
|
m_float_emit.STR(32, INDEX_UNSIGNED, D31, dst_reg, m_dst_ofs + 8);
|
|
|
|
m_dst_ofs += sizeof(float) * 3;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Prepare for the next vertex.
|
|
ADD(dst_reg, dst_reg, m_dst_ofs);
|
|
const u8* cont = GetCodePtr();
|
|
ADD(src_reg, src_reg, m_src_ofs);
|
|
|
|
SUB(count_reg, count_reg, 1);
|
|
CBNZ(count_reg, loop_start);
|
|
|
|
if (m_VtxDesc.Position & MASK_INDEXED)
|
|
{
|
|
SUB(W0, saved_count, skipped_reg);
|
|
RET(X30);
|
|
|
|
SetJumpTarget(m_skip_vertex);
|
|
ADD(skipped_reg, skipped_reg, 1);
|
|
B(cont);
|
|
}
|
|
else
|
|
{
|
|
MOV(W0, saved_count);
|
|
RET(X30);
|
|
}
|
|
|
|
FlushIcache();
|
|
|
|
m_VertexSize = m_src_ofs;
|
|
m_native_vtx_decl.stride = m_dst_ofs;
|
|
}
|
|
|
|
int VertexLoaderARM64::RunVertices(DataReader src, DataReader dst, int count)
|
|
{
|
|
m_numLoadedVertices += count;
|
|
return ((int (*)(u8* src, u8* dst, int count))region)(src.GetPointer(), dst.GetPointer(), count);
|
|
}
|