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https://github.com/dolphin-emu/dolphin.git
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0a606d7356
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6095 8ced0084-cf51-0410-be5f-012b33b47a6e
64 lines
2.0 KiB
C
64 lines
2.0 KiB
C
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#ifndef _DSPREGS_H
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#define _DSPREGS_H
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#define DSP_REG_AR0 0x00 // address registers
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#define DSP_REG_AR1 0x01
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#define DSP_REG_AR2 0x02
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#define DSP_REG_AR3 0x03
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#define DSP_REG_IX0 0x04 // indexing registers (actually, mostly used as increments)
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#define DSP_REG_IX1 0x05
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#define DSP_REG_IX2 0x06
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#define DSP_REG_IX3 0x07
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#define DSP_REG_WR0 0x08 // address wrapping registers. should be initialized to 0xFFFF if not used.
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#define DSP_REG_WR1 0x09
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#define DSP_REG_WR2 0x0a
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#define DSP_REG_WR3 0x0b
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#define DSP_REG_ST0 0x0c // stacks.
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#define DSP_REG_ST1 0x0d
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#define DSP_REG_ST2 0x0e
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#define DSP_REG_ST3 0x0f
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#define DSP_REG_CR 0x12 // Seems to be the top 8 bits of LRS/SRS.
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#define DSP_REG_SR 0x13
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#define DSP_REG_PRODL 0x14 // product.
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#define DSP_REG_PRODM 0x15
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#define DSP_REG_PRODH 0x16
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#define DSP_REG_PRODM2 0x17
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#define DSP_REG_AXL0 0x18
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#define DSP_REG_AXL1 0x19
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#define DSP_REG_AXH0 0x1a
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#define DSP_REG_AXH1 0x1b
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#define DSP_REG_ACC0 0x1c // accumulator (global)
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#define DSP_REG_ACC1 0x1d
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#define DSP_REG_ACL0 0x1c // Low accumulator
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#define DSP_REG_ACL1 0x1d
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#define DSP_REG_ACM0 0x1e // Mid accumulator
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#define DSP_REG_ACM1 0x1f
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#define DSP_REG_ACH0 0x10 // Sign extended 8 bit register 0
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#define DSP_REG_ACH1 0x11 // Sign extended 8 bit register 1
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#endif |