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https://github.com/dolphin-emu/dolphin.git
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d05e205a24
The workaround of using fixed underlying types produces lots of warnings in GCC because now the bit-fields are too small for the value range used for conversion semantics.
123 lines
3.1 KiB
C++
123 lines
3.1 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "Common/Common.h"
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#include "Common/CPUDetect.h"
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#include "Common/FPURoundMode.h"
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#ifdef _WIN32
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# include <mmintrin.h>
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#else
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# include <xmmintrin.h>
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#endif
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namespace FPURoundMode
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{
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// Get the default SSE states here.
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static u32 saved_sse_state = _mm_getcsr();
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static const u32 default_sse_state = _mm_getcsr();
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void SetRoundMode(int mode)
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{
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// Set FPU rounding mode to mimic the PowerPC's
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#ifdef _M_X86_32
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// This shouldn't really be needed anymore since we use SSE
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#ifdef _WIN32
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const int table[4] =
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{
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_RC_NEAR,
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_RC_CHOP,
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_RC_UP,
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_RC_DOWN
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};
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_set_controlfp(_MCW_RC, table[mode]);
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#else
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const unsigned short X87_ROUND_MASK = 3 << 10;
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const unsigned short x87_rounding_table[] =
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{
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0 << 10, // nearest
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3 << 10, // zero
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2 << 10, // +inf
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1 << 10, // -inf
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};
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unsigned short _mode;
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asm ("fstcw %0" : "=m" (_mode));
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_mode = (_mode & ~X87_ROUND_MASK) | x87_rounding_table[mode];
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asm ("fldcw %0" : : "m" (_mode));
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#endif
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#endif
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}
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void SetPrecisionMode(PrecisionMode mode)
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{
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#ifdef _M_X86_32
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// sets the floating-point lib to 53-bit
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// PowerPC has a 53bit floating pipeline only
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// eg: sscanf is very sensitive
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#ifdef _WIN32
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_control87(_PC_53, MCW_PC);
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#else
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const unsigned short PRECISION_MASK = 3 << 8;
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const unsigned short precision_table[] = {
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0 << 8, // 24 bits
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2 << 8, // 53 bits
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3 << 8, // 64 bits
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};
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unsigned short _mode;
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asm ("fstcw %0" : "=m" (_mode));
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_mode = (_mode & ~PRECISION_MASK) | precision_table[mode];
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asm ("fldcw %0" : : "m" (_mode));
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#endif
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#else
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//x64 doesn't need this - fpu is done with SSE
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//but still - set any useful sse options here
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#endif
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}
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void SetSIMDMode(int rounding_mode, bool non_ieee_mode)
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{
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// OR-mask for disabling FPU exceptions (bits 7-12 in the MXCSR register)
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const u32 EXCEPTION_MASK = 0x1F80;
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// Denormals-Are-Zero (non-IEEE mode: denormal inputs are set to +/- 0)
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const u32 DAZ = 0x40;
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// Flush-To-Zero (non-IEEE mode: denormal outputs are set to +/- 0)
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const u32 FTZ = 0x8000;
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// lookup table for FPSCR.RN-to-MXCSR.RC translation
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static const u32 simd_rounding_table[] =
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{
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(0 << 13) | EXCEPTION_MASK, // nearest
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(3 << 13) | EXCEPTION_MASK, // -inf
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(2 << 13) | EXCEPTION_MASK, // +inf
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(1 << 13) | EXCEPTION_MASK, // zero
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};
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u32 csr = simd_rounding_table[rounding_mode];
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// Some initial steppings of Pentium 4 CPUs support FTZ but not DAZ.
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// They will not flush input operands but flushing outputs only is better than nothing.
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static const u32 denormalLUT[2] =
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{
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FTZ, // flush-to-zero only
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FTZ | DAZ, // flush-to-zero and denormals-are-zero (may not be supported)
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};
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if (non_ieee_mode)
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{
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csr |= denormalLUT[cpu_info.bFlushToZero];
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}
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_mm_setcsr(csr);
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}
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void SaveSIMDState()
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{
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saved_sse_state = _mm_getcsr();
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}
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void LoadSIMDState()
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{
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_mm_setcsr(saved_sse_state);
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}
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void LoadDefaultSIMDState()
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{
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_mm_setcsr(default_sse_state);
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}
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}
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