mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-15 05:47:56 -07:00
80710984dc
- Moves all test code from DSPTool into UnitTests/Core/DSPAssemblyTest. - Converts test files (which could only be loaded if they were in the shell's working directory, so basically never) into C++ values. - Enables most of the commented-out tests. - Removes non-deterministic random code test.
647 lines
8.4 KiB
C++
647 lines
8.4 KiB
C++
// Copyright 2017 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include "DSPTestText.h"
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const char s_dsp_test_text[8434] = R"(
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DSCR: equ 0xffc9 ; DSP DMA Control Reg
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DSBL: equ 0xffcb ; DSP DMA Block Length
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DSPA: equ 0xffcd ; DSP DMA DMEM Address
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DSMAH: equ 0xffce ; DSP DMA Mem Address H
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DSMAL: equ 0xffcf ; DSP DMA Mem Address L
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ACSAH: equ 0xffd4
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ACSAL: equ 0xffd5
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ACEAH: equ 0xffd6
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ACEAL: equ 0xffd7
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ACCAH: equ 0xffd8
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ACCAL: equ 0xffd9
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AMDM: equ 0xffef ; ARAM DMA Request Mask
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DIRQ: equ 0xfffb ; DSP Irq Request
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DMBH: equ 0xfffc ; DSP Mailbox H
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DMBL: equ 0xfffd ; DSP Mailbox L
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CMBH: equ 0xfffe ; CPU Mailbox H
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CMBL: equ 0xffff ; CPU Mailbox L
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R00: equ 0x00
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R01: equ 0x01
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R02: equ 0x02
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R03: equ 0x03
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R04: equ 0x04
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R05: equ 0x05
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R06: equ 0x06
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R07: equ 0x07
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R08: equ 0x08
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R09: equ 0x09
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R0A: equ 0x0a
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R0B: equ 0x0b
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R0C: equ 0x0c
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R0D: equ 0x0d
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R0E: equ 0x0e
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R0F: equ 0x0f
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R10: equ 0x10
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R11: equ 0x11
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R12: equ 0x12
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R13: equ 0x13
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R14: equ 0x14
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R15: equ 0x15
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R16: equ 0x16
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R17: equ 0x17
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R18: equ 0x18
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R19: equ 0x19
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R1A: equ 0x1a
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R1B: equ 0x1b
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R1C: equ 0x1c
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R1D: equ 0x1d
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R1E: equ 0x1e
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R1F: equ 0x1f
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ACH0: equ 0x10
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ACH1: equ 0x11
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ACL0: equ 0x1e
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ACL1: equ 0x1f
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DSP_CR_IMEM: equ 2
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DSP_CR_TO_CPU: equ 1
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REGS_BASE: equ 0x0f80
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MEM_HI: equ 0x0f7E
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MEM_LO: equ 0x0f7F
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; Interrupt vectors 8 vectors, 2 opcodes each
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jmp irq0
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jmp irq1
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jmp irq2
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jmp irq3
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jmp irq4
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jmp irq5
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jmp irq6
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jmp irq7
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; Main code at 0x10
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CW 0x1302
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CW 0x1303
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CW 0x1204
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CW 0x1305
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CW 0x1306
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s40
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lri $r12, #0x00ff
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main:
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cw 0x8900
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cw 0x8100
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; get address of memory dump and copy it
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBL, #0xdead
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si @DIRQ, #0x0001
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call wait_for_cpu_mbox
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lrs $ACL0, @CMBL
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andi $acl1, #0x7fff
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sr @MEM_HI, $ACL1
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sr @MEM_LO, $ACL0
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lri $r18, #0
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lri $r19, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $r1a, #0x2000
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lr $r1c, @MEM_HI
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lr $r1e, @MEM_LO
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call do_dma
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; get address of registers and DMA them to memory
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBL, #0xbeef
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si @DIRQ, #0x0001
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call wait_for_cpu_mbox
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lrs $ACL0, @CMBL
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andi $acl1, #0x7fff
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sr @MEM_HI, $ACL1
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sr @MEM_LO, $ACL0
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lri $r18, #REGS_BASE
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lri $r19, #0 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $r1a, #0x80
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lr $r1c, @MEM_HI
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lr $r1e, @MEM_LO
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call do_dma
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lri $r00, #REGS_BASE+1
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lrri $r01, @$r00
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lrri $r02, @$r00
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lrri $r03, @$r00
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lrri $r04, @$r00
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lrri $r05, @$r00
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lrri $r06, @$r00
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lrri $r07, @$r00
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lrri $r08, @$r00
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lrri $r09, @$r00
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lrri $r0a, @$r00
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lrri $r0b, @$r00
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lrri $r0c, @$r00
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lrri $r0d, @$r00
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lrri $r0e, @$r00
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lrri $r0f, @$r00
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lrri $r10, @$r00
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lrri $r11, @$r00
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lrri $r12, @$r00
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lrri $r13, @$r00
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lrri $r14, @$r00
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lrri $r15, @$r00
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lrri $r16, @$r00
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lrri $r17, @$r00
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lrri $r18, @$r00
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lrri $r19, @$r00
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lrri $r1a, @$r00
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lrri $r1b, @$r00
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lrri $r1c, @$r00
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lrri $r1d, @$r00
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lrri $r1e, @$r00
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lrri $r1f, @$r00
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lr $r00, @REGS_BASE
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nop
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nop
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nop
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nop
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cw 0x8600
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call send_back
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JMP ende
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; call dump_memory
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; call send_back
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; 0x041e
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;
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cw 0x00de
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cw 0x03f1
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call send_back
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cw 0x0200
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cw 0x0a60
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call send_back
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cw 0x1c7e
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call send_back
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cw 0x8100
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call send_back
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cw 0x8900
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call send_back
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cw 0x009f
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cw 0x00a0
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call send_back
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cw 0x00de
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cw 0x03f1
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call send_back
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cw 0x5d00
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call send_back
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cw 0x0e50
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call send_back
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cw 0x0750
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call send_back
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cw 0x0270
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call send_back
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cw 0x5d00
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call send_back
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cw 0x00da
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cw 0x03f2
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call send_back
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cw 0x8600
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call send_back
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JGE g_0c4d
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; cw 0x0290
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; cw 0x0c4d
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; call send_back JX0
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cw 0x00de
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cw 0x03f3
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call send_back
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cw 0x5c00
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call send_back
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JLE g_0c38
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; cw 0x0293
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; cw 0x0c38 JX3
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; call send_back
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JMP g_0c52
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; cw 0x029f
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; cw 0x0c52
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; call send_back
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g_0c38:
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cw 0x00db
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cw 0x03f7
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call send_back
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cw 0x009e
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cw 0x8000
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call send_back
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cw 0x4600
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call send_back
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JMP g_0c44
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; cw 0x029f
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; cw 0x0c44
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; call send_back
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g_0c3f:
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cw 0x00db
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cw 0x03f7
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call send_back
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cw 0x009e
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cw 0x8000
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call send_back
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cw 0x5600
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call send_back
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g_0c44:
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cw 0x00fe
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cw 0x03f5
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call send_back
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cw 0x1fda
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call send_back
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cw 0x7c00
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call send_back
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cw 0x1f5e
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call send_back
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cw 0x00fe
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cw 0x03f2
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call send_back
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JMP g_0c52
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; cw 0x029f
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; cw 0x0c52
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; call send_back
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g_0c4d:
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cw 0x00de
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cw 0x03f4
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call send_back
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cw 0x5d00
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call send_back
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JLE g_0c3f
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; cw 0x0293
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; cw 0x0c3f
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; call send_back
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g_0c52:
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cw 0x8900
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call send_back
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cw 0x00dd
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cw 0x03f5
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call send_back
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cw 0x1501
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call send_back
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cw 0x8100
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call send_back
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cw 0x00dc
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cw 0x03f6
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call send_back
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cw 0x008b
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cw 0x009f
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call send_back
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cw 0x0080
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cw 0x0a00
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call send_back
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cw 0x0900
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call send_back
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BLOOPI #0x50, g_0c65
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; cw 0x1150
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; cw 0x0c65
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; call send_back
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cw 0x1878
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call send_back
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cw 0x4c00
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call send_back
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cw 0x1cfe
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call send_back
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cw 0x001f
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call send_back
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cw 0x1fd9
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call send_back
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g_0c65:
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cw 0x1b18
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call send_back
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cw 0x009f
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cw 0x0a60
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call send_back
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cw 0x1fc3
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call send_back
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cw 0x5c00
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call send_back
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cw 0x00fe
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cw 0x03f1
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call send_back
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cw 0x00fc
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cw 0x03f6
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call send_back
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cw 0x008b
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cw 0xffff
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call send_back
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ende:
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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dead_loop:
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jmp dead_loop
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do_dma:
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sr @DSMAH, $r1c
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sr @DSMAL, $r1e
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sr @DSPA, $r18
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sr @DSCR, $r19
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sr @DSBL, $r1a
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wait_dma:
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LRS $ACL1, @DSCR
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andcf $acl1, #0x0004
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JLZ wait_dma
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RET
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wait_for_dsp_mbox:
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lrs $ACL1, @DMBH
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andcf $acl1, #0x8000
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jlz wait_for_dsp_mbox
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ret
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wait_for_cpu_mbox:
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lrs $ACL1, @cmbh
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andcf $acl1, #0x8000
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jlnz wait_for_cpu_mbox
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ret
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irq0:
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lri $acl0, #0x0000
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jmp irq
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irq1:
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lri $acl0, #0x0001
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jmp irq
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irq2:
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lri $acl0, #0x0002
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jmp irq
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irq3:
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lri $acl0, #0x0003
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jmp irq
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irq4:
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lri $acl0, #0x0004
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jmp irq
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irq5:
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; jmp finale
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s40
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mrr $r0d, $r1c
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mrr $r0d, $r1e
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clr $acc0
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mrr $r1e, $r0d
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mrr $r1c, $r0d
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nop
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nop
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nop
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nop
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nop
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nop
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rti
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lri $acl0, #0x0005
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jmp irq
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irq6:
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lri $acl0, #0x0006
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jmp irq
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irq7:
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lri $acl0, #0x0007
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jmp irq
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irq:
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lrs $ACL1, @DMBH
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andcf $acl1, #0x8000
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jlz irq
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si @DMBH, #0x8BAD
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sr @DMBL, $r0b
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;sr @DMBL, $acl0
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si @DIRQ, #0x0001
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halt
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send_back:
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; store registers to reg table
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sr @REGS_BASE, $r00
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lri $r00, #(REGS_BASE + 1)
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srri @$r00, $r01
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srri @$r00, $r02
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srri @$r00, $r03
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srri @$r00, $r04
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srri @$r00, $r05
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srri @$r00, $r06
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srri @$r00, $r07
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srri @$r00, $r08
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srri @$r00, $r09
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srri @$r00, $r0a
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srri @$r00, $r0b
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srri @$r00, $r0c
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srri @$r00, $r0d
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srri @$r00, $r0e
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srri @$r00, $r0f
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srri @$r00, $r10
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srri @$r00, $r11
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srri @$r00, $r12
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srri @$r00, $r13
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srri @$r00, $r14
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srri @$r00, $r15
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srri @$r00, $r16
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srri @$r00, $r17
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srri @$r00, $r18
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srri @$r00, $r19
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srri @$r00, $r1a
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srri @$r00, $r1b
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srri @$r00, $r1c
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srri @$r00, $r1d
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srri @$r00, $r1e
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srri @$r00, $r1f
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lri $r18, #0x0000
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lri $r19, #1 ;(DSP_CR_IMEM | DSP_CR_TO_CPU)
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lri $r1a, #0x200
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lr $r1c, @MEM_HI
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lr $r1e, @MEM_LO
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lri $r01, #8+8
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bloop $r01, dma_copy
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call do_dma
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addi $r1e, #0x200
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mrr $r1f, $r18
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addi $r1f, #0x100
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mrr $r18, $r1f
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nop
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dma_copy:
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nop
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call wait_for_dsp_mbox
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si @DMBH, #0x8888
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si @DMBL, #0xfeeb
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si @DIRQ, #0x0001
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; wait for answer before we execute the next op
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call wait_for_cpu_mbox
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lrs $ACL0, @CMBL
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andi $acl1, #0x7fff
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lri $r00, #REGS_BASE+1
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lrri $r01, @$r00
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lrri $r02, @$r00
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lrri $r03, @$r00
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lrri $r04, @$r00
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lrri $r05, @$r00
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lrri $r06, @$r00
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lrri $r07, @$r00
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lrri $r08, @$r00
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lrri $r09, @$r00
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lrri $r0a, @$r00
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lrri $r0b, @$r00
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lrri $r0c, @$r00
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lrri $r0d, @$r00
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lrri $r0e, @$r00
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lrri $r0f, @$r00
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lrri $r10, @$r00
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lrri $r11, @$r00
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lrri $r12, @$r00
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lrri $r13, @$r00
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lrri $r14, @$r00
|
|
lrri $r15, @$r00
|
|
lrri $r16, @$r00
|
|
lrri $r17, @$r00
|
|
lrri $r18, @$r00
|
|
lrri $r19, @$r00
|
|
lrri $r1a, @$r00
|
|
lrri $r1b, @$r00
|
|
lrri $r1c, @$r00
|
|
lrri $r1d, @$r00
|
|
lrri $r1e, @$r00
|
|
lrri $r1f, @$r00
|
|
lr $r00, @REGS_BASE
|
|
|
|
ret
|
|
|
|
send_back_16:
|
|
|
|
cw 0x8e00
|
|
call send_back
|
|
cw 0x8f00
|
|
|
|
ret
|
|
|
|
|
|
dump_memory:
|
|
|
|
lri $r02, #0x0000
|
|
lri $acl0, #0x1000
|
|
|
|
lri $r01, #0x1000
|
|
bloop $r01, _fill_loop2
|
|
|
|
mrr $r03, $acl0
|
|
cw 0x80f0
|
|
|
|
mrr $r1f, $r00
|
|
mrr $r00, $r02
|
|
srri @$r00, $r1b
|
|
mrr $r02, $r00
|
|
mrr $r00, $r1f
|
|
|
|
addis $AC0.M, #0x1
|
|
|
|
_fill_loop2:
|
|
nop
|
|
|
|
|
|
ret
|
|
)";
|