2025-01-30 21:59:05 -07:00
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#include <cpu.h>
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#include <bus.h>
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#include <emu.h>
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extern cpu_context ctx;
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void fetch_data() {
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ctx.mem_dest = 0;
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ctx.dest_is_mem = false;
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if(ctx.cur_inst == NULL) return;
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switch(ctx.cur_inst->mode) {
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case AM_IMP: return;
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case AM_R:
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ctx.fetched_data = cpu_read_reg(ctx.cur_inst->reg_1);
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return;
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case AM_R_R:
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ctx.fetched_data = cpu_read_reg(ctx.cur_inst->reg_2);
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2025-01-30 22:54:33 -07:00
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return;
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2025-01-30 21:59:05 -07:00
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case AM_R_D8:
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ctx.fetched_data = bus_read(ctx.regs.pc);
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emu_cycles(1);
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ctx.regs.pc++;
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return;
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case AM_R_D16:
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case AM_D16: {
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u16 lo = bus_read(ctx.regs.pc);
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emu_cycles(1);
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u16 hi = bus_read(ctx.regs.pc+1);
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emu_cycles(1);
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ctx.fetched_data = lo | (hi << 8);
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ctx.regs.pc += 2;
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return;
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}
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case AM_MR_R:
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ctx.fetched_data = cpu_read_reg(ctx.cur_inst->reg_2);
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ctx.mem_dest = cpu_read_reg(ctx.cur_inst->reg_1);
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ctx.dest_is_mem = true;
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if (ctx.cur_inst->reg_1 == RT_C) {
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ctx.mem_dest |= 0xFF00;
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}
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return;
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case AM_R_MR: {
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u16 addr = cpu_read_reg(ctx.cur_inst->reg_2);
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2025-02-01 00:48:49 -07:00
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if(ctx.cur_inst->reg_2 == RT_C) {
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2025-01-30 21:59:05 -07:00
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addr |= 0xFF00;
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}
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ctx.fetched_data = bus_read(addr);
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emu_cycles(1);
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return;
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}
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case AM_R_HLI:
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ctx.fetched_data = bus_read(cpu_read_reg(ctx.cur_inst->reg_2));
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emu_cycles(1);
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cpu_set_reg(RT_HL, cpu_read_reg(RT_HL)+1);
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return;
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case AM_R_HLD:
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ctx.fetched_data = bus_read(cpu_read_reg(ctx.cur_inst->reg_2));
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emu_cycles(1);
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cpu_set_reg(RT_HL, cpu_read_reg(RT_HL)-1);
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return;
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case AM_HLI_R:
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ctx.fetched_data = cpu_read_reg(ctx.cur_inst->reg_2);
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2025-01-31 17:07:09 -07:00
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ctx.mem_dest = cpu_read_reg(ctx.cur_inst->reg_1);
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2025-01-30 21:59:05 -07:00
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ctx.dest_is_mem = true;
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cpu_set_reg(RT_HL, cpu_read_reg(RT_HL)+1);
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return;
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case AM_HLD_R:
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ctx.fetched_data = cpu_read_reg(ctx.cur_inst->reg_2);
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ctx.mem_dest = cpu_read_reg(ctx.cur_inst->reg_1);
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ctx.dest_is_mem = true;
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cpu_set_reg(RT_HL, cpu_read_reg(RT_HL)-1);
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return;
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case AM_R_A8:
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2025-02-01 00:48:49 -07:00
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ctx.fetched_data = bus_read(ctx.regs.pc);
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2025-01-30 21:59:05 -07:00
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emu_cycles(2);
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ctx.regs.pc++;
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return;
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case AM_A8_R:
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ctx.mem_dest = bus_read(ctx.regs.pc) | 0xFF00;
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emu_cycles(1);
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ctx.dest_is_mem = true;
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ctx.regs.pc++;
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return;
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case AM_HL_SPR:
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ctx.fetched_data = bus_read(ctx.regs.pc);
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emu_cycles(1);
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ctx.regs.pc++;
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return;
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case AM_D8:
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ctx.fetched_data = bus_read(ctx.regs.pc);
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emu_cycles(1);
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ctx.regs.pc++;
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return;
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case AM_A16_R:
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case AM_D16_R: {
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u16 lo = bus_read(ctx.regs.pc);
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emu_cycles(1);
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u16 hi = bus_read(ctx.regs.pc+1);
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emu_cycles(1);
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ctx.mem_dest = lo | (hi << 8);
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ctx.dest_is_mem = true;
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ctx.regs.pc += 2;
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ctx.fetched_data = cpu_read_reg(ctx.cur_inst->reg_2);
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} return;
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case AM_MR_D8:
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ctx.fetched_data = bus_read(ctx.regs.pc);
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emu_cycles(1);
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ctx.regs.pc++;
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ctx.mem_dest = cpu_read_reg(ctx.cur_inst->reg_1);
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ctx.dest_is_mem = true;
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return;
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case AM_MR:
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ctx.mem_dest = cpu_read_reg(ctx.cur_inst->reg_1);
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ctx.dest_is_mem = true;
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ctx.fetched_data = bus_read(cpu_read_reg(ctx.cur_inst->reg_1));
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emu_cycles(1);
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return;
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case AM_R_A16: {
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u16 lo = bus_read(ctx.regs.pc);
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emu_cycles(1);
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u16 hi = bus_read(ctx.regs.pc+1);
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emu_cycles(1);
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ctx.fetched_data = bus_read(lo | (hi << 8));
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emu_cycles(1);
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ctx.regs.pc += 2;
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} return;
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default:
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printf("Unknown Addressing Mode! %d (%02X)\n", ctx.cur_inst->mode, ctx.cur_opcode);
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exit(-7);
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return;
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}
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}
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