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dma and mbc1 passing

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This commit is contained in:
Samuel Walker
2025-05-30 11:15:21 -06:00
parent 1455bc5666
commit 26b1f10e16
7 changed files with 76 additions and 23 deletions
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2
.vscode/launch.json vendored
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@ -9,7 +9,7 @@
"request": "launch",
"name": "Debug",
"program": "${workspaceFolder}/build/gbemu/Debug/gbemu.exe",
"args": [ "${workspaceFolder}/roms/cpu_instrs.gb" ],
"args": [ "C:\\Users\\piwalker\\Downloads\\mts-20240926-1737-443f6e1\\mts-20240926-1737-443f6e1\\emulator-only\\mbc1\\rom_512kb.gb" ],
"cwd": "${workspaceFolder}"
}
]

1
include/cart.h
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@ -24,6 +24,7 @@ typedef struct {
u32 rom_size;
u8 *rom_data;
rom_header *header;
bool is_multicart;
//mbc1 data
bool ram_enabled;

2
lib/bus.c
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@ -81,6 +81,8 @@ void bus_write(u16 address, u8 value) {
//OAM
if(!dma_transferring())
ppu_oam_write(address, value);
else
printf("ACCESS DURING DMA!\n");
return;
} else if (address < 0xFF00) {
//reserved unusable

72
lib/cart.c
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@ -250,6 +250,25 @@ bool cart_load(char *cart) {
fprintf(stderr, "WARNING!!! The header checksum does not match! ROM may be corrupt or invalid!\n");
}
if(cart_mbc1() && ctx.header->rom_size >= 5) {
int count = 0;
for(int i = 1; i < 4; i++) {
u32 start_addr = (i << 18);
bool same = true;
for(int j = 0x104; j < 0x134; j++) {
if(ctx.rom_data[start_addr | j] != ctx.rom_data[j]) {
same = false;
break;
}
}
if(same)
count++;
}
if(count >= 2) {
ctx.is_multicart = true;
}
}
if(ctx.battery) {
cart_battery_load();
}
@ -294,38 +313,66 @@ void cart_write(u16 address, u8 value){
if((address & 0xE000) == 0x2000) {
//rom bank
if(value == 0) {
value = 1;
}
if(cart_mbc3()) {
value &= 0b1111111;
if(value == 0) {
value = 1;
}
ctx.rom_bank_value = value;
ctx.rom_bank_x = ctx.rom_data + (0x4000 * ctx.rom_bank_value);
}else {
//printf("Bank Value: %d\n", value);
value &= 0b11111;
if(value == 0) {
value = 1;
}
if(ctx.is_multicart)
value &= 0b1111;
//printf("Bank Value after filter: %d\n", value);
switch(ctx.header->rom_size) {
case 0: value &= 0b1; break;
case 1: value &= 0b11; break;
case 2: value &= 0b111; break;
case 3: value &= 0b1111; break;
default: break;
}
ctx.rom_bank_value = value;
if(ctx.header->rom_size >= 5) {
ctx.rom_bank_x = ctx.rom_data + (0x4000 * (ctx.rom_bank_value+ctx.rom_bank_value_2));
//printf("(REG1 >5) Banked %d\n", ctx.rom_bank_value+ctx.rom_bank_value_2);
return;
}
ctx.rom_bank_x = ctx.rom_data + (0x4000 * ctx.rom_bank_value);
//printf("(REG1 <5) Banked %d\n", ctx.rom_bank_value);
}
}
if((address & 0xE000) == 0x4000) {
//ram bank number
if(cart_mbc1() && ctx.banking_mode && ctx.header->rom_size >= 5) {
if(cart_mbc1() && ctx.header->rom_size >= 5) {
if(ctx.header->rom_size == 5)
value &= 0b1;
ctx.rom_bank_value_2 = (value & 0b11) << 5;
if(ctx.is_multicart)
ctx.rom_bank_value_2 = (value & 0b11) << 4;
ctx.rom_bank_x = ctx.rom_data + (0x4000 * (ctx.rom_bank_value+ctx.rom_bank_value_2));
ctx.rom_bank_x2 = ctx.rom_data + (0x4000 * (ctx.rom_bank_value_2));
//printf("(REG2 >5) Banked %d\n", ctx.rom_bank_value+ctx.rom_bank_value_2);
if(ctx.banking_mode)
ctx.rom_bank_x2 = ctx.rom_data + (0x4000 * (ctx.rom_bank_value_2));
return;
}
ctx.ram_bank_value = value & 0b11;
if(ctx.ram_banking) {
if(cart_need_save) {
if(cart_need_save()) {
cart_battery_save();
}
ctx.ram_bank = ctx.ram_banks[ctx.ram_bank_value];
if((ctx.header->ram_size == 2 && ctx.ram_bank_value == 0) ||
(ctx.header->ram_size == 3 && ctx.ram_bank_value < 4) ||
(ctx.header->ram_size == 5 && ctx.ram_bank_value < 8) ||
(ctx.header->ram_size == 4)) {
ctx.ram_bank = ctx.ram_banks[ctx.ram_bank_value];
}
}
}
@ -349,10 +396,17 @@ void cart_write(u16 address, u8 value){
}
if (ctx.ram_banking) {
if(cart_need_save) {
if(cart_need_save()) {
cart_battery_save();
}
ctx.ram_bank = ctx.ram_banks[ctx.ram_bank_value];
if((ctx.header->ram_size == 2 && ctx.ram_bank_value == 0) ||
(ctx.header->ram_size == 3 && ctx.ram_bank_value < 4) ||
(ctx.header->ram_size == 5 && ctx.ram_bank_value < 8) ||
(ctx.header->ram_size == 4)) {
ctx.ram_bank = ctx.ram_banks[ctx.ram_bank_value];
}
} else {
ctx.ram_bank = ctx.ram_banks[0];
}
}
}

14
lib/cpu.c
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@ -8,7 +8,7 @@
#include <memory.h>
cpu_context ctx = {0};
#define CPU_DEBUG 0
#define CPU_DEBUG 1
#define FILE_LOG 0
#if FILE_LOG == 1
@ -55,10 +55,6 @@ static void execute() {
bool cpu_step() {
if(ctx.regs.pc == 0x4348) {
printf("made it!\n");
}
if(!ctx.halted) {
u16 pc = ctx.regs.pc;
fetch_instruction();
@ -81,15 +77,15 @@ bool cpu_step() {
char inst[16];
inst_to_str(&ctx, inst);
printf("%08lX - %04X: %-12s (%02X %02X %02X) A: %02X F: %s BC: %02X%02X DE: %02X%02X HL: %02X%02X SP: %04X PC: %04X\n", emu_get_context()->ticks, pc, inst, ctx.cur_opcode, bus_read(pc+1), bus_read(pc+2), ctx.regs.a, flags, ctx.regs.b, ctx.regs.c, ctx.regs.d, ctx.regs.e, ctx.regs.h, ctx.regs.l, ctx.regs.sp, ctx.regs.pc);
//printf("%-12s\n", inst);
//printf("%08lX - %04X: %-12s (%02X %02X %02X) A: %02X F: %s BC: %02X%02X DE: %02X%02X HL: %02X%02X SP: %04X PC: %04X\n", emu_get_context()->ticks, pc, inst, ctx.cur_opcode, bus_read(pc+1), bus_read(pc+2), ctx.regs.a, flags, ctx.regs.b, ctx.regs.c, ctx.regs.d, ctx.regs.e, ctx.regs.h, ctx.regs.l, ctx.regs.sp, ctx.regs.pc);
if(ctx.cur_inst == NULL){
printf("Unknown Instruction! %02X\n", ctx.cur_opcode);
exit(-7);
}
dbg_update();
dbg_print();
//dbg_update();
//dbg_print();
#endif
execute();

4
lib/dma.c
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@ -7,7 +7,7 @@ static dma_context ctx;
void dma_start(u8 start) {
ctx.active = true;
ctx.byte = 0;
ctx.start_delay = 2;
ctx.start_delay = 0;
ctx.value = start;
}
@ -21,7 +21,7 @@ void dma_tick() {
return;
}
ppu_oam_write(ctx.byte, bus_read(((ctx.value << 8)) + ctx.byte));
ppu_oam_write(ctx.byte, bus_read((ctx.value << 8) | ctx.byte));
ctx.byte++;

2
lib/ppu.c
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@ -70,7 +70,7 @@ void ppu_oam_write(u16 address, u8 value) {
}
u8 ppu_oam_read(u16 address){
if (address > 0xFE00) {
if (address >= 0xFE00) {
address -= 0xFE00;
}