2016-11-02 18:38:58 -06:00
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// ARM shit
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#ifndef ARM_H
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#define ARM_H
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#include "types.h"
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#include "NDS.h"
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2016-11-24 10:31:49 -07:00
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// lame
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#define C_S(x) x
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#define C_N(x) x
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2016-11-24 16:08:53 -07:00
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#define C_I(x) x
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#define ROR(x, n) (((x) >> (n)) | ((x) << (32-(n))))
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2016-11-24 10:31:49 -07:00
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2016-11-02 18:38:58 -06:00
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class ARM
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{
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public:
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ARM(u32 num);
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~ARM(); // destroy shit
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2016-11-24 10:31:49 -07:00
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void Reset();
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2016-11-02 18:38:58 -06:00
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void JumpTo(u32 addr);
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2016-11-24 16:08:53 -07:00
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void RestoreCPSR();
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2016-11-02 18:38:58 -06:00
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s32 Execute(s32 cycles);
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2016-11-24 16:08:53 -07:00
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bool CheckCondition(u32 code)
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{
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if (code == 0xE) return true;
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if (ConditionTable[code] & (1 << (CPSR>>28))) return true;
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return false;
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}
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void SetC(bool c)
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{
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if (c) CPSR |= 0x20000000;
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else CPSR &= ~0x20000000;
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}
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void SetNZ(bool n, bool z)
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{
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CPSR &= ~0xC0000000;
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if (n) CPSR |= 0x80000000;
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if (z) CPSR |= 0x40000000;
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}
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void SetNZCV(bool n, bool z, bool c, bool v)
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{
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CPSR &= ~0xF0000000;
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if (n) CPSR |= 0x80000000;
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if (z) CPSR |= 0x40000000;
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if (c) CPSR |= 0x20000000;
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if (v) CPSR |= 0x10000000;
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}
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2016-12-02 17:31:33 -07:00
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u8 Read8(u32 addr, u32 forceuser=0)
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{
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if (!Num)
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{
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// TODO: PU shit
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return NDS::ARM9Read8(addr);
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}
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else
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return NDS::ARM7Read8(addr);
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}
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u16 Read16(u32 addr, u32 forceuser=0)
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2016-11-02 18:38:58 -06:00
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{
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2016-12-02 17:31:33 -07:00
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addr &= ~1;
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if (!Num)
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{
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// TODO: PU shit
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return NDS::ARM9Read16(addr);
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}
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else
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return NDS::ARM7Read16(addr);
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}
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u32 Read32(u32 addr, u32 forceuser=0)
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{
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addr &= ~3;
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if (!Num)
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{
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// TODO: PU shit
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return NDS::ARM9Read32(addr);
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}
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else
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return NDS::ARM7Read32(addr);
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}
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void Write8(u32 addr, u8 val, u32 forceuser=0)
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{
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if (!Num)
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{
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// TODO: PU shit
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NDS::ARM9Write8(addr, val);
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}
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else
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NDS::ARM7Write8(addr, val);
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}
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void Write16(u32 addr, u16 val, u32 forceuser=0)
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{
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addr &= ~1;
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if (!Num)
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{
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// TODO: PU shit
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NDS::ARM9Write16(addr, val);
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}
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else
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NDS::ARM7Write16(addr, val);
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}
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void Write32(u32 addr, u32 val, u32 forceuser=0)
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{
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addr &= ~3;
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if (!Num)
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{
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// TODO: PU shit
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NDS::ARM9Write32(addr, val);
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}
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else
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NDS::ARM7Write32(addr, val);
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}
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s32 MemWaitstate(u32 type, u32 addr)
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{
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// type:
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// 0 = code16
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// 1 = code32
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// 2 = data16
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// 3 = data32
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return 1; // sorry
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2016-11-02 18:38:58 -06:00
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}
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u32 Num;
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u32 R[16]; // heh
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u32 CPSR;
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u32 R_FIQ[8]; // holding SPSR too
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u32 R_SVC[3];
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u32 R_ABT[3];
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u32 R_IRQ[3];
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u32 R_UND[3];
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u32 CurInstr;
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u32 NextInstr;
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u32 ExceptionBase;
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2016-11-24 16:08:53 -07:00
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static u32 ConditionTable[16];
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2016-11-02 18:38:58 -06:00
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};
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#endif // ARM_H
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