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improve ldm timings

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I believe this also applies to other loads as well, but currently untested.
This commit is contained in:
Jaklyy
2024-06-24 19:44:38 -04:00
parent 3583d8222f
commit 109bbed3d0
3 changed files with 67 additions and 20 deletions
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19
src/CP15.cpp
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@ -815,22 +815,23 @@ bool ARMv5::DataRead8(u32 addr, u32* val)
return false;
}
DataRegion = addr;
if (addr < ITCMSize)
{
DataRegion = Mem9_ITCM;
DataCycles = 1;
*val = *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataRegion = Mem9_DTCM;
DataCycles = 1;
*val = *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return true;
}
*val = BusRead8(addr);
DataRegion = NDS.ARM9Regions[addr >> 14];
DataCycles = MemTimings[addr >> 12][1];
return true;
}
@ -843,24 +844,25 @@ bool ARMv5::DataRead16(u32 addr, u32* val)
return false;
}
DataRegion = addr;
addr &= ~1;
if (addr < ITCMSize)
{
DataRegion = Mem9_ITCM;
DataCycles = 1;
*val = *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataRegion = Mem9_DTCM;
DataCycles = 1;
*val = *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return true;
}
*val = BusRead16(addr);
DataRegion = NDS.ARM9Regions[addr >> 14];
DataCycles = MemTimings[addr >> 12][1];
return true;
}
@ -873,24 +875,25 @@ bool ARMv5::DataRead32(u32 addr, u32* val)
return false;
}
DataRegion = addr;
addr &= ~3;
if (addr < ITCMSize)
{
DataRegion = Mem9_ITCM;
DataCycles = 1;
*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataRegion = Mem9_DTCM;
DataCycles = 1;
*val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return true;
}
*val = BusRead32(addr);
DataRegion = NDS.ARM9Regions[addr >> 14];
DataCycles = MemTimings[addr >> 12][2];
return true;
}