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https://github.com/melonDS-emu/melonDS.git
synced 2025-07-25 07:10:00 -06:00
JIT: most mem instructions working
+ branching
This commit is contained in:
RSDuck
@ -9,7 +9,7 @@ using namespace Gen;
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namespace ARMJIT
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{
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template <>
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const X64Reg RegCache<Compiler, X64Reg>::NativeRegAllocOrder[] =
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const X64Reg RegCache<Compiler, X64Reg>::NativeRegAllocOrder[] =
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{
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#ifdef _WIN32
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RBX, RSI, RDI, R12, R13
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@ -18,7 +18,7 @@ const X64Reg RegCache<Compiler, X64Reg>::NativeRegAllocOrder[] =
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#endif
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};
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template <>
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const int RegCache<Compiler, X64Reg>::NativeRegsAvailable =
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const int RegCache<Compiler, X64Reg>::NativeRegsAvailable =
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#ifdef _WIN32
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5
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#else
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@ -30,24 +30,33 @@ Compiler::Compiler()
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{
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AllocCodeSpace(1024 * 1024 * 16);
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for (int i = 0; i < 15; i++)
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for (int i = 0; i < 3; i++)
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{
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ReadMemFuncs9[i] = Gen_MemoryRoutine9(false, 32, 0x1000000 * i);
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WriteMemFuncs9[i] = Gen_MemoryRoutine9(true, 32, 0x1000000 * i);
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for (int j = 0; j < 2; j++)
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{
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ReadMemFuncs7[j][i] = Gen_MemoryRoutine7(false, 32, j, 0x1000000 * i);
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WriteMemFuncs7[j][i] = Gen_MemoryRoutine7(true, 32, j, 0x1000000 * i);
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MemoryFuncs9[i][j] = Gen_MemoryRoutine9(j, 8 << i);
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MemoryFuncs7[i][j][0] = Gen_MemoryRoutine7(j, false, 8 << i);
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MemoryFuncs7[i][j][1] = Gen_MemoryRoutine7(j, true, 8 << i);
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}
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}
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ReadMemFuncs9[15] = Gen_MemoryRoutine9(false, 32, 0xFF000000);
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WriteMemFuncs9[15] = Gen_MemoryRoutine9(true, 32, 0xFF000000);
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ReadMemFuncs7[15][0] = ReadMemFuncs7[15][1] = Gen_MemoryRoutine7(false, 32, false, 0xFF000000);
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WriteMemFuncs7[15][0] = WriteMemFuncs7[15][1] = Gen_MemoryRoutine7(true, 32, false, 0xFF000000);
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ResetStart = GetWritableCodePtr();
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}
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DataRegion Compiler::ClassifyAddress(u32 addr)
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{
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if (Num == 0 && addr >= ((ARMv5*)CurCPU)->DTCMBase && addr < ((ARMv5*)CurCPU)->DTCMBase)
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return dataRegionDTCM;
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switch (addr & 0xFF000000)
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{
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case 0x02000000: return dataRegionMainRAM;
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case 0x03000000: return Num == 1 && (addr & 0xF00000) == 0x800000 ? dataRegionWRAM7 : dataRegionSWRAM;
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case 0x04000000: return dataRegionIO;
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case 0x06000000: return dataRegionVRAM;
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}
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return dataRegionGeneric;
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}
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void Compiler::LoadCPSR()
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{
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assert(!CPSRDirty);
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@ -92,6 +101,7 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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Num = cpu->Num;
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R15 = cpu->R[15];
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CodeRegion = cpu->CodeRegion;
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CurCPU = cpu;
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ABI_PushRegistersAndAdjustStack({ABI_ALL_CALLEE_SAVED & ABI_ALL_GPRS}, 8, 16);
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@ -106,27 +116,32 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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for (int i = 0; i < instrsCount; i++)
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{
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R15 += Thumb ? 2 : 4;
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CurrentInstr = instrs[i];
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CurInstr = instrs[i];
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CompileFunc comp = GetCompFunc(CurrentInstr.Info.Kind);
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if (CurrentInstr.Info.Branches())
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comp = NULL;
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CompileFunc comp = GetCompFunc(CurInstr.Info.Kind);
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if (comp == NULL || i == instrsCount - 1)
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{
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MOV(32, MDisp(RCPU, offsetof(ARM, R[15])), Imm32(R15));
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MOV(32, MDisp(RCPU, offsetof(ARM, CodeCycles)), Imm32(CurrentInstr.CodeCycles));
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MOV(32, MDisp(RCPU, offsetof(ARM, CurInstr)), Imm32(CurrentInstr.Instr));
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MOV(32, MDisp(RCPU, offsetof(ARM, CodeCycles)), Imm32(CurInstr.CodeCycles));
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MOV(32, MDisp(RCPU, offsetof(ARM, CurInstr)), Imm32(CurInstr.Instr));
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if (i == instrsCount - 1)
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{
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MOV(32, MDisp(RCPU, offsetof(ARM, NextInstr[0])), Imm32(CurrentInstr.NextInstr[0]));
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MOV(32, MDisp(RCPU, offsetof(ARM, NextInstr[1])), Imm32(CurrentInstr.NextInstr[1]));
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MOV(32, MDisp(RCPU, offsetof(ARM, NextInstr[0])), Imm32(CurInstr.NextInstr[0]));
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MOV(32, MDisp(RCPU, offsetof(ARM, NextInstr[1])), Imm32(CurInstr.NextInstr[1]));
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}
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SaveCPSR();
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if (comp == NULL || CurInstr.Info.Branches())
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SaveCPSR();
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}
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// run interpreter
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cpu->CodeCycles = CurInstr.CodeCycles;
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cpu->R[15] = R15;
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cpu->CurInstr = CurInstr.Instr;
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cpu->NextInstr[0] = CurInstr.NextInstr[0];
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cpu->NextInstr[1] = CurInstr.NextInstr[1];
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if (comp != NULL)
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RegCache.Prepare(i);
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else
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@ -134,26 +149,33 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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if (Thumb)
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{
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u32 icode = (CurInstr.Instr >> 6) & 0x3FF;
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if (comp == NULL)
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{
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MOV(64, R(ABI_PARAM1), R(RCPU));
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u32 icode = (CurrentInstr.Instr >> 6) & 0x3FF;
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ABI_CallFunction(ARMInterpreter::THUMBInstrTable[icode]);
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}
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else
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(this->*comp)();
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ARMInterpreter::THUMBInstrTable[icode](cpu);
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}
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else
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{
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u32 cond = CurrentInstr.Cond();
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if (CurrentInstr.Info.Kind == ARMInstrInfo::ak_BLX_IMM)
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u32 cond = CurInstr.Cond();
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if (CurInstr.Info.Kind == ARMInstrInfo::ak_BLX_IMM)
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{
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MOV(64, R(ABI_PARAM1), R(RCPU));
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ABI_CallFunction(ARMInterpreter::A_BLX_IMM);
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ARMInterpreter::A_BLX_IMM(cpu);
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}
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else if (cond == 0xF)
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{
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Comp_AddCycles_C();
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cpu->AddCycles_C();
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}
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else
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{
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FixupBranch skipExecute;
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@ -180,18 +202,18 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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}
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u32 icode = ((CurInstr.Instr >> 4) & 0xF) | ((CurInstr.Instr >> 16) & 0xFF0);
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if (comp == NULL)
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{
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MOV(64, R(ABI_PARAM1), R(RCPU));
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u32 icode = ((CurrentInstr.Instr >> 4) & 0xF) | ((CurrentInstr.Instr >> 16) & 0xFF0);
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ABI_CallFunction(ARMInterpreter::ARMInstrTable[icode]);
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}
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else
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(this->*comp)();
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FixupBranch skipFailed;
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if (CurrentInstr.Cond() < 0xE)
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if (CurInstr.Cond() < 0xE)
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{
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skipFailed = J();
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SetJumpTarget(skipExecute);
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@ -200,13 +222,17 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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SetJumpTarget(skipFailed);
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}
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if (cpu->CheckCondition(cond))
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ARMInterpreter::ARMInstrTable[icode](cpu);
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else
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cpu->AddCycles_C();
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}
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}
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/*
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we don't need to collect the interpreted cycles,
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since all functions only add to it, the dispatcher
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takes care of it.
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since cpu->Cycles is taken into account by the dispatcher.
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*/
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if (comp == NULL && i != instrsCount - 1)
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@ -277,29 +303,29 @@ CompileFunc Compiler::GetCompFunc(int kind)
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// Mul
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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// ARMv5 stuff
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NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL,
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// STR
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A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB,
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// STRB
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB,
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// LDR
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A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB,
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// LDRB
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB, A_Comp_MemWB,
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// STRH
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NULL, NULL, NULL, NULL,
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A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf,
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// LDRD
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NULL, NULL, NULL, NULL,
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// STRD
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NULL, NULL, NULL, NULL,
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// LDRH
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NULL, NULL, NULL, NULL,
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A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf,
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// LDRSB
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NULL, NULL, NULL, NULL,
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A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf,
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// LDRSH
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NULL, NULL, NULL, NULL,
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A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf, A_Comp_MemHalf,
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// swap
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NULL, NULL,
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NULL, NULL,
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// LDM/STM
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NULL, NULL,
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// Branch
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@ -314,26 +340,26 @@ CompileFunc Compiler::GetCompFunc(int kind)
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// Three operand ADD/SUB
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T_Comp_AddSub_, T_Comp_AddSub_, T_Comp_AddSub_, T_Comp_AddSub_,
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// 8 bit imm
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T_Comp_ALU_Imm8, T_Comp_ALU_Imm8, T_Comp_ALU_Imm8, T_Comp_ALU_Imm8,
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T_Comp_ALU_Imm8, T_Comp_ALU_Imm8, T_Comp_ALU_Imm8, T_Comp_ALU_Imm8,
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// general ALU
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, NULL, T_Comp_ALU, T_Comp_ALU,
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// hi reg
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T_Comp_ALU_HiReg, T_Comp_ALU_HiReg, T_Comp_ALU_HiReg,
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// pc/sp relative
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NULL, NULL, NULL,
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T_Comp_RelAddr, T_Comp_RelAddr, T_Comp_AddSP,
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// LDR pcrel
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NULL,
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NULL,
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// LDR/STR reg offset
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T_Comp_MemReg, NULL, T_Comp_MemReg, NULL,
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// LDR/STR sign extended, half
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NULL, NULL, NULL, NULL,
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T_Comp_MemReg, T_Comp_MemReg, T_Comp_MemReg, T_Comp_MemReg,
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// LDR/STR sign extended, half
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T_Comp_MemRegHalf, T_Comp_MemRegHalf, T_Comp_MemRegHalf, T_Comp_MemRegHalf,
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// LDR/STR imm offset
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T_Comp_MemImm, T_Comp_MemImm, NULL, NULL,
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T_Comp_MemImm, T_Comp_MemImm, T_Comp_MemImm, T_Comp_MemImm,
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// LDR/STR half imm offset
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NULL, NULL,
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T_Comp_MemImmHalf, T_Comp_MemImmHalf,
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// branch, etc.
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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@ -346,10 +372,10 @@ CompileFunc Compiler::GetCompFunc(int kind)
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void Compiler::Comp_AddCycles_C()
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{
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s32 cycles = Num ?
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NDS::ARM7MemTimings[CurrentInstr.CodeCycles][Thumb ? 1 : 3]
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: ((R15 & 0x2) ? 0 : CurrentInstr.CodeCycles);
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NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 1 : 3]
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: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles);
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if (CurrentInstr.Cond() < 0xE)
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if (CurInstr.Cond() < 0xE)
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ADD(32, R(RCycles), Imm8(cycles));
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else
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ConstantCycles += cycles;
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@ -358,13 +384,26 @@ void Compiler::Comp_AddCycles_C()
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void Compiler::Comp_AddCycles_CI(u32 i)
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{
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s32 cycles = (Num ?
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NDS::ARM7MemTimings[CurrentInstr.CodeCycles][Thumb ? 0 : 2]
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: ((R15 & 0x2) ? 0 : CurrentInstr.CodeCycles)) + i;
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if (CurrentInstr.Cond() < 0xE)
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NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2]
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: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles)) + i;
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if (CurInstr.Cond() < 0xE)
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ADD(32, R(RCycles), Imm8(cycles));
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else
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ConstantCycles += cycles;
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}
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void Compiler::Comp_JumpTo(Gen::X64Reg addr, bool restoreCPSR)
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{
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SaveCPSR();
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MOV(64, R(ABI_PARAM1), R(RCPU));
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MOV(32, R(ABI_PARAM2), R(addr));
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MOV(32, R(ABI_PARAM3), Imm32(restoreCPSR));
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if (Num == 0)
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CALL((void*)&ARMv5::JumpTo);
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else
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CALL((void*)&ARMv4::JumpTo);
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}
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}
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