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more accurate DTCM check

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Arisotura
2021-10-28 22:41:42 +02:00
parent 43daa1c7d2
commit 15a66b1be1
3 changed files with 41 additions and 36 deletions
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2
src/ARM.h
View File

@ -269,7 +269,7 @@ public:
// for aarch64 JIT they need to go up here // for aarch64 JIT they need to go up here
// to be addressable by a 12-bit immediate // to be addressable by a 12-bit immediate
u32 ITCMSize; u32 ITCMSize;
u32 DTCMBase, DTCMSize; u32 DTCMBase, DTCMMask, DTCMSize;
s32 RegionCodeCycles; s32 RegionCodeCycles;
u8 ITCM[ITCMPhysicalSize]; u8 ITCM[ITCMPhysicalSize];

22
src/ARMJIT.cpp
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@ -179,8 +179,8 @@ T SlowRead9(u32 addr, ARMv5* cpu)
T val; T val;
if (addr < cpu->ITCMSize) if (addr < cpu->ITCMSize)
val = *(T*)&cpu->ITCM[addr & 0x7FFF]; val = *(T*)&cpu->ITCM[addr & 0x7FFF];
else if (addr >= cpu->DTCMBase && addr < (cpu->DTCMBase + cpu->DTCMSize)) else if ((addr & cpu->DTCMMask) == cpu->DTCMBase)
val = *(T*)&cpu->DTCM[(addr - cpu->DTCMBase) & 0x3FFF]; val = *(T*)&cpu->DTCM[addr & 0x3FFF];
else if (std::is_same<T, u32>::value) else if (std::is_same<T, u32>::value)
val = (ConsoleType == 0 ? NDS::ARM9Read32 : DSi::ARM9Read32)(addr); val = (ConsoleType == 0 ? NDS::ARM9Read32 : DSi::ARM9Read32)(addr);
else if (std::is_same<T, u16>::value) else if (std::is_same<T, u16>::value)
@ -204,9 +204,9 @@ void SlowWrite9(u32 addr, ARMv5* cpu, u32 val)
CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr); CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
*(T*)&cpu->ITCM[addr & 0x7FFF] = val; *(T*)&cpu->ITCM[addr & 0x7FFF] = val;
} }
else if (addr >= cpu->DTCMBase && addr < (cpu->DTCMBase + cpu->DTCMSize)) else if ((addr & cpu->DTCMMask) == cpu->DTCMBase)
{ {
*(T*)&cpu->DTCM[(addr - cpu->DTCMBase) & 0x3FFF] = val; *(T*)&cpu->DTCM[addr & 0x3FFF] = val;
} }
else if (std::is_same<T, u32>::value) else if (std::is_same<T, u32>::value)
{ {
@ -377,7 +377,7 @@ bool DecodeLiteral(bool thumb, const FetchedInstr& instr, u32& addr)
return false; return false;
} }
bool DecodeBranch(bool thumb, const FetchedInstr& instr, u32& cond, bool hasLink, u32 lr, bool& link, bool DecodeBranch(bool thumb, const FetchedInstr& instr, u32& cond, bool hasLink, u32 lr, bool& link,
u32& linkAddr, u32& targetAddr) u32& linkAddr, u32& targetAddr)
{ {
if (thumb) if (thumb)
@ -420,7 +420,7 @@ bool DecodeBranch(bool thumb, const FetchedInstr& instr, u32& cond, bool hasLink
linkAddr = instr.Addr + 4; linkAddr = instr.Addr + 4;
cond = instr.Cond(); cond = instr.Cond();
if (instr.Info.Kind == ARMInstrInfo::ak_BL if (instr.Info.Kind == ARMInstrInfo::ak_BL
|| instr.Info.Kind == ARMInstrInfo::ak_B) || instr.Info.Kind == ARMInstrInfo::ak_B)
{ {
s32 offset = (s32)(instr.Instr << 8) >> 6; s32 offset = (s32)(instr.Instr << 8) >> 6;
@ -461,7 +461,7 @@ bool IsIdleLoop(bool thumb, FetchedInstr* instrs, int instrsCount)
u16 dstRegs = instrs[i].Info.DstRegs & ~(1 << 15); u16 dstRegs = instrs[i].Info.DstRegs & ~(1 << 15);
regsDisallowedToWrite |= srcRegs & ~regsWrittenTo; regsDisallowedToWrite |= srcRegs & ~regsWrittenTo;
if (dstRegs & regsDisallowedToWrite) if (dstRegs & regsDisallowedToWrite)
return false; return false;
regsWrittenTo |= dstRegs; regsWrittenTo |= dstRegs;
@ -551,7 +551,7 @@ InterpreterFunc InterpretTHUMB[ARMInstrInfo::tk_Count] =
F(LDRB_IMM), F(STRH_IMM), F(LDRH_IMM), F(STR_SPREL), F(LDR_SPREL), F(LDRB_IMM), F(STRH_IMM), F(LDRH_IMM), F(STR_SPREL), F(LDR_SPREL),
F(PUSH), F(POP), F(LDMIA), F(STMIA), F(PUSH), F(POP), F(LDMIA), F(STMIA),
F(BCOND), F(BX), F(BLX_REG), F(B), F(BL_LONG_1), F(BL_LONG_2), F(BCOND), F(BX), F(BLX_REG), F(B), F(BL_LONG_1), F(BL_LONG_2),
F(UNK), F(SVC), F(UNK), F(SVC),
T_BL_LONG // BL_LONG psudo opcode T_BL_LONG // BL_LONG psudo opcode
}; };
#undef F #undef F
@ -607,7 +607,7 @@ void CompileBlock(ARM* cpu)
} }
// some memory has been remapped // some memory has been remapped
RetireJitBlock(existingBlockIt->second); RetireJitBlock(existingBlockIt->second);
map.erase(existingBlockIt); map.erase(existingBlockIt);
} }
@ -830,7 +830,7 @@ void CompileBlock(ARM* cpu)
lr = linkAddr; lr = linkAddr;
hasLink = true; hasLink = true;
} }
r15 = target + (thumb ? 2 : 4); r15 = target + (thumb ? 2 : 4);
assert(r15 == cpu->R[15]); assert(r15 == cpu->R[15]);
@ -940,7 +940,7 @@ void CompileBlock(ARM* cpu)
block->StartAddrLocal = localAddr; block->StartAddrLocal = localAddr;
FloodFillSetFlags(instrs, i - 1, 0xF); FloodFillSetFlags(instrs, i - 1, 0xF);
JitEnableWrite(); JitEnableWrite();
block->EntryPoint = JITCompiler->CompileBlock(cpu, thumb, instrs, i, hasMemoryInstr); block->EntryPoint = JITCompiler->CompileBlock(cpu, thumb, instrs, i, hasMemoryInstr);
JitEnableExecute(); JitEnableExecute();

53
src/CP15.cpp
View File

@ -50,6 +50,7 @@ void ARMv5::CP15Reset()
ITCMSize = 0; ITCMSize = 0;
DTCMBase = 0xFFFFFFFF; DTCMBase = 0xFFFFFFFF;
DTCMMask = 0;
DTCMSize = 0; DTCMSize = 0;
memset(ICache, 0, 0x2000); memset(ICache, 0, 0x2000);
@ -102,25 +103,29 @@ void ARMv5::CP15DoSavestate(Savestate* file)
void ARMv5::UpdateDTCMSetting() void ARMv5::UpdateDTCMSetting()
{ {
u32 newDTCMBase; u32 newDTCMBase;
u32 newDTCMMask;
u32 newDTCMSize; u32 newDTCMSize;
if (CP15Control & (1<<16)) if (CP15Control & (1<<16))
{ {
newDTCMBase = DTCMSetting & 0xFFFFF000;
newDTCMSize = 0x200 << ((DTCMSetting >> 1) & 0x1F); newDTCMSize = 0x200 << ((DTCMSetting >> 1) & 0x1F);
//printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, newDTCMBase, newDTCMSize); newDTCMMask = 0xFFFFF000 & ~(newDTCMSize-1);
newDTCMBase = DTCMSetting & newDTCMMask;
} }
else else
{ {
newDTCMBase = 0xFFFFFFFF;
newDTCMSize = 0; newDTCMSize = 0;
//printf("DTCM disabled\n"); newDTCMBase = 0xFFFFFFFF;
newDTCMMask = 0;
} }
if (newDTCMBase != DTCMBase || newDTCMSize != DTCMSize)
if (newDTCMBase != DTCMBase || newDTCMMask != DTCMMask)
{ {
#ifdef JIT_ENABLED #ifdef JIT_ENABLED
ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMSize); ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMMask);
#endif #endif
DTCMBase = newDTCMBase; DTCMBase = newDTCMBase;
DTCMMask = newDTCMMask;
DTCMSize = newDTCMSize; DTCMSize = newDTCMSize;
} }
} }
@ -600,12 +605,12 @@ void ARMv5::CP15Write(u32 id, u32 val)
case 0x910: case 0x910:
DTCMSetting = val; DTCMSetting = val & 0xFFFFF03E;
UpdateDTCMSetting(); UpdateDTCMSetting();
return; return;
case 0x911: case 0x911:
ITCMSetting = val; ITCMSetting = val & 0x0000003E;
UpdateITCMSetting(); UpdateITCMSetting();
return; return;
@ -774,10 +779,10 @@ void ARMv5::DataRead8(u32 addr, u32* val)
*val = *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)]; *val = *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles = 1; DataCycles = 1;
*val = *(u8*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; *val = *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return; return;
} }
@ -797,10 +802,10 @@ void ARMv5::DataRead16(u32 addr, u32* val)
*val = *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)]; *val = *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles = 1; DataCycles = 1;
*val = *(u16*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; *val = *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return; return;
} }
@ -826,10 +831,10 @@ void ARMv5::DataRead32(u32 addr, u32* val)
*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)]; *val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles = 1; DataCycles = 1;
*val = *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; *val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return; return;
} }
@ -847,10 +852,10 @@ void ARMv5::DataRead32S(u32 addr, u32* val)
*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)]; *val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles += 1; DataCycles += 1;
*val = *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)]; *val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return; return;
} }
@ -871,10 +876,10 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
#endif #endif
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles = 1; DataCycles = 1;
*(u8*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return; return;
} }
@ -897,10 +902,10 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
#endif #endif
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles = 1; DataCycles = 1;
*(u16*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return; return;
} }
@ -929,10 +934,10 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
#endif #endif
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles = 1; DataCycles = 1;
*(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return; return;
} }
@ -953,10 +958,10 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
#endif #endif
return; return;
} }
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize)) if ((addr & DTCMMask) == DTCMBase)
{ {
DataCycles += 1; DataCycles += 1;
*(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val; *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return; return;
} }