piwalker/melonDS
1
0
Fork 0
mirror of https://github.com/melonDS-emu/melonDS.git synced 2025-07-23 06:10:03 -06:00
Code Issues Packages Projects Releases Wiki Activity

more accurate DTCM check

Browse Source
This commit is contained in:
Arisotura
2021-10-28 22:41:42 +02:00
parent 43daa1c7d2
commit 15a66b1be1
3 changed files with 41 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/ARM.h
View File

@ -269,7 +269,7 @@ public:
// for aarch64 JIT they need to go up here
// to be addressable by a 12-bit immediate
u32 ITCMSize;
u32 DTCMBase, DTCMSize;
u32 DTCMBase, DTCMMask, DTCMSize;
s32 RegionCodeCycles;
u8 ITCM[ITCMPhysicalSize];

8
src/ARMJIT.cpp
View File

@ -179,8 +179,8 @@ T SlowRead9(u32 addr, ARMv5* cpu)
T val;
if (addr < cpu->ITCMSize)
val = *(T*)&cpu->ITCM[addr & 0x7FFF];
else if (addr >= cpu->DTCMBase && addr < (cpu->DTCMBase + cpu->DTCMSize))
val = *(T*)&cpu->DTCM[(addr - cpu->DTCMBase) & 0x3FFF];
else if ((addr & cpu->DTCMMask) == cpu->DTCMBase)
val = *(T*)&cpu->DTCM[addr & 0x3FFF];
else if (std::is_same<T, u32>::value)
val = (ConsoleType == 0 ? NDS::ARM9Read32 : DSi::ARM9Read32)(addr);
else if (std::is_same<T, u16>::value)
@ -204,9 +204,9 @@ void SlowWrite9(u32 addr, ARMv5* cpu, u32 val)
CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
*(T*)&cpu->ITCM[addr & 0x7FFF] = val;
}
else if (addr >= cpu->DTCMBase && addr < (cpu->DTCMBase + cpu->DTCMSize))
else if ((addr & cpu->DTCMMask) == cpu->DTCMBase)
{
*(T*)&cpu->DTCM[(addr - cpu->DTCMBase) & 0x3FFF] = val;
*(T*)&cpu->DTCM[addr & 0x3FFF] = val;
}
else if (std::is_same<T, u32>::value)
{

53
src/CP15.cpp
View File

@ -50,6 +50,7 @@ void ARMv5::CP15Reset()
ITCMSize = 0;
DTCMBase = 0xFFFFFFFF;
DTCMMask = 0;
DTCMSize = 0;
memset(ICache, 0, 0x2000);
@ -102,25 +103,29 @@ void ARMv5::CP15DoSavestate(Savestate* file)
void ARMv5::UpdateDTCMSetting()
{
u32 newDTCMBase;
u32 newDTCMMask;
u32 newDTCMSize;
if (CP15Control & (1<<16))
{
newDTCMBase = DTCMSetting & 0xFFFFF000;
newDTCMSize = 0x200 << ((DTCMSetting >> 1) & 0x1F);
//printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, newDTCMBase, newDTCMSize);
newDTCMMask = 0xFFFFF000 & ~(newDTCMSize-1);
newDTCMBase = DTCMSetting & newDTCMMask;
}
else
{
newDTCMBase = 0xFFFFFFFF;
newDTCMSize = 0;
//printf("DTCM disabled\n");
newDTCMBase = 0xFFFFFFFF;
newDTCMMask = 0;
}
if (newDTCMBase != DTCMBase || newDTCMSize != DTCMSize)
if (newDTCMBase != DTCMBase || newDTCMMask != DTCMMask)
{
#ifdef JIT_ENABLED
ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMSize);
ARMJIT_Memory::RemapDTCM(newDTCMBase, newDTCMMask);
#endif
DTCMBase = newDTCMBase;
DTCMMask = newDTCMMask;
DTCMSize = newDTCMSize;
}
}
@ -600,12 +605,12 @@ void ARMv5::CP15Write(u32 id, u32 val)
case 0x910:
DTCMSetting = val;
DTCMSetting = val & 0xFFFFF03E;
UpdateDTCMSetting();
return;
case 0x911:
ITCMSetting = val;
ITCMSetting = val & 0x0000003E;
UpdateITCMSetting();
return;
@ -774,10 +779,10 @@ void ARMv5::DataRead8(u32 addr, u32* val)
*val = *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*val = *(u8*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)];
*val = *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return;
}
@ -797,10 +802,10 @@ void ARMv5::DataRead16(u32 addr, u32* val)
*val = *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*val = *(u16*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)];
*val = *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return;
}
@ -826,10 +831,10 @@ void ARMv5::DataRead32(u32 addr, u32* val)
*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*val = *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)];
*val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return;
}
@ -847,10 +852,10 @@ void ARMv5::DataRead32S(u32 addr, u32* val)
*val = *(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles += 1;
*val = *(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)];
*val = *(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return;
}
@ -871,10 +876,10 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
#endif
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*(u8*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val;
*(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
}
@ -897,10 +902,10 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
#endif
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*(u16*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val;
*(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
}
@ -929,10 +934,10 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
#endif
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val;
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
}
@ -953,10 +958,10 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
#endif
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles += 1;
*(u32*)&DTCM[(addr - DTCMBase) & (DTCMPhysicalSize - 1)] = val;
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
}