mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-25 23:29:55 -06:00
begin work on general timing renovation. way shitty because it behaves as if caches were off, so everything will be slow as shit.
This commit is contained in:
StapleButter
417
src/ARM.h
417
src/ARM.h
@ -19,24 +19,29 @@
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#ifndef ARM_H
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#define ARM_H
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#include <algorithm>
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#include "types.h"
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#include "NDS.h"
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#include "CP15.h"
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// lame
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#define C_S(x) x
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#define C_N(x) x
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#define C_I(x) x
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#define ROR(x, n) (((x) >> (n)) | ((x) << (32-(n))))
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enum
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{
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RWFlags_Nonseq = (1<<5),
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RWFlags_ForceUser = (1<<21),
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};
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class ARM
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{
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public:
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ARM(u32 num);
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~ARM(); // destroy shit
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void Reset();
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virtual void Reset();
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virtual void DoSavestate(Savestate* file);
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void SetClockShift(u32 shift)
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{
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@ -44,9 +49,9 @@ public:
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ClockDiffMask = (1<<shift) - 1;
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}
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void DoSavestate(Savestate* file);
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virtual void CalculateTimings() = 0;
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void JumpTo(u32 addr, bool restorecpsr = false);
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virtual void JumpTo(u32 addr, bool restorecpsr = false) = 0;
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void RestoreCPSR();
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void Halt(u32 halt)
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@ -55,6 +60,7 @@ public:
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Halted = halt;
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}
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// TODO: is this actually used??
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void CheckIRQ()
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{
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if (!(NDS::IME[Num] & 0x1)) return;
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@ -64,7 +70,7 @@ public:
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}
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}
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s32 Execute();
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virtual s32 Execute() = 0;
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bool CheckCondition(u32 code)
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{
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@ -102,133 +108,17 @@ public:
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void SetupCodeMem(u32 addr);
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u16 CodeRead16(u32 addr)
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{
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Cycles += Waitstates[0][(addr>>24)&0xF];
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virtual bool DataRead8(u32 addr, u32* val, u32 flags) = 0;
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virtual bool DataRead16(u32 addr, u32* val, u32 flags) = 0;
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virtual bool DataRead32(u32 addr, u32* val, u32 flags) = 0;
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virtual bool DataWrite8(u32 addr, u8 val, u32 flags) = 0;
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virtual bool DataWrite16(u32 addr, u16 val, u32 flags) = 0;
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virtual bool DataWrite32(u32 addr, u32 val, u32 flags) = 0;
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if (CodeMem.Mem) return *(u16*)&CodeMem.Mem[addr & CodeMem.Mask];
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u16 val;
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// TODO eventually: on ARM9, THUMB opcodes are prefetched with 32bit reads
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// probably not worth going through the trouble. we can probably just simulate
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// the timing quirks resulting from this. or not.
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if (!Num)
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{
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if (!CP15::HandleCodeRead16(addr, &val))
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val = NDS::ARM9Read16(addr);
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}
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else
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val = NDS::ARM7Read16(addr);
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return val;
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}
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u32 CodeRead32(u32 addr)
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{
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Cycles += Waitstates[1][(addr>>24)&0xF];
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if (CodeMem.Mem) return *(u32*)&CodeMem.Mem[addr & CodeMem.Mask];
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u32 val;
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if (!Num)
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{
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if (!CP15::HandleCodeRead32(addr, &val))
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val = NDS::ARM9Read32(addr);
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}
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else
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val = NDS::ARM7Read32(addr);
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return val;
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}
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u8 DataRead8(u32 addr, u32 forceuser=0)
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{
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u8 val;
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if (!Num)
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{
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if (!CP15::HandleDataRead8(addr, &val, forceuser))
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val = NDS::ARM9Read8(addr);
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}
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else
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val = NDS::ARM7Read8(addr);
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Cycles += Waitstates[2][(addr>>24)&0xF];
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return val;
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}
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u16 DataRead16(u32 addr, u32 forceuser=0)
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{
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u16 val;
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addr &= ~1;
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if (!Num)
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{
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if (!CP15::HandleDataRead16(addr, &val, forceuser))
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val = NDS::ARM9Read16(addr);
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}
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else
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val = NDS::ARM7Read16(addr);
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Cycles += Waitstates[2][(addr>>24)&0xF];
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return val;
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}
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u32 DataRead32(u32 addr, u32 forceuser=0)
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{
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u32 val;
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addr &= ~3;
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if (!Num)
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{
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if (!CP15::HandleDataRead32(addr, &val, forceuser))
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val = NDS::ARM9Read32(addr);
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}
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else
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val = NDS::ARM7Read32(addr);
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Cycles += Waitstates[3][(addr>>24)&0xF];
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return val;
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}
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void DataWrite8(u32 addr, u8 val, u32 forceuser=0)
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{
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if (!Num)
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{
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if (!CP15::HandleDataWrite8(addr, val, forceuser))
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NDS::ARM9Write8(addr, val);
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}
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else
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NDS::ARM7Write8(addr, val);
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Cycles += Waitstates[2][(addr>>24)&0xF];
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}
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void DataWrite16(u32 addr, u16 val, u32 forceuser=0)
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{
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addr &= ~1;
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if (!Num)
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{
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if (!CP15::HandleDataWrite16(addr, val, forceuser))
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NDS::ARM9Write16(addr, val);
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}
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else
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NDS::ARM7Write16(addr, val);
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Cycles += Waitstates[2][(addr>>24)&0xF];
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}
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void DataWrite32(u32 addr, u32 val, u32 forceuser=0)
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{
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addr &= ~3;
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if (!Num)
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{
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if (!CP15::HandleDataWrite32(addr, val, forceuser))
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NDS::ARM9Write32(addr, val);
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}
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else
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NDS::ARM7Write32(addr, val);
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Cycles += Waitstates[3][(addr>>24)&0xF];
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}
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virtual void AddCycles_C() = 0;
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virtual void AddCycles_CI(s32 num) = 0;
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virtual void AddCycles_CDI() = 0;
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virtual void AddCycles_CD() = 0;
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u32 Num;
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@ -238,16 +128,15 @@ public:
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u32 ClockShift;
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u32 ClockDiffMask;
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// waitstates:
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// 0=code16 1=code32 2=data16 3=data32
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// TODO eventually: nonsequential waitstates
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// TODO NOT MAKE THIS A FUCKING GROSS HACK!!!!!!
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s32 Waitstates[4][16];
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s32 Cycles;
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s32 CyclesToRun;
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u32 Halted;
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int CodeRegion;
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int DataRegion;
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s32 DataCycles;
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u32 R[16]; // heh
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u32 CPSR;
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u32 R_FIQ[8]; // holding SPSR too
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@ -265,6 +154,252 @@ public:
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static u32 ConditionTable[16];
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};
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class ARMv5 : public ARM
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{
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public:
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ARMv5();
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void Reset();
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void DoSavestate(Savestate* file);
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void CalculateTimings();
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void JumpTo(u32 addr, bool restorecpsr = false);
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s32 Execute();
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// all code accesses are forced nonseq 32bit
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u32 CodeRead32(u32 addr);
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bool DataRead8(u32 addr, u32* val, u32 flags);
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bool DataRead16(u32 addr, u32* val, u32 flags);
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bool DataRead32(u32 addr, u32* val, u32 flags);
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bool DataWrite8(u32 addr, u8 val, u32 flags);
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bool DataWrite16(u32 addr, u16 val, u32 flags);
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bool DataWrite32(u32 addr, u32 val, u32 flags);
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void AddCycles_C()
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{
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// code only. always nonseq 32-bit for ARM9.
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Cycles += NDS::ARM9MemTimings[CodeRegion][2];
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}
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void AddCycles_CI(s32 num)
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{
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// code+internal
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Cycles += NDS::ARM9MemTimings[CodeRegion][2] + num;
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}
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void AddCycles_CDI()
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{
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// LDR/LDM cycles. ARM9 seems to skip the internal cycle there.
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// TODO: ITCM data fetches shouldn't be parallelized, they say
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s32 numC = NDS::ARM9MemTimings[CodeRegion][2];
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s32 numD = DataCycles;
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if (DataRegion != CodeRegion)
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Cycles += std::max(numC + numD - 6, std::max(numC, numD));
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else
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Cycles += numC + numD;
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}
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void AddCycles_CD()
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{
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// TODO: ITCM data fetches shouldn't be parallelized, they say
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s32 numC = NDS::ARM9MemTimings[CodeRegion][2];
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s32 numD = DataCycles;
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if (DataRegion != CodeRegion)
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Cycles += std::max(numC + numD - 6, std::max(numC, numD));
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else
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Cycles += numC + numD;
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}
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void GetCodeMemRegion(u32 addr, NDS::MemRegion* region);
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void CP15Reset();
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void CP15DoSavestate(Savestate* file);
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void UpdateDTCMSetting();
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void UpdateITCMSetting();
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void CP15Write(u32 id, u32 val);
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u32 CP15Read(u32 id);
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u32 CP15Control;
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u32 DTCMSetting, ITCMSetting;
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u8 ITCM[0x8000];
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u32 ITCMSize;
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u8 DTCM[0x4000];
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u32 DTCMBase, DTCMSize;
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};
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class ARMv4 : public ARM
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{
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public:
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ARMv4();
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void CalculateTimings();
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void JumpTo(u32 addr, bool restorecpsr = false);
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s32 Execute();
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u16 CodeRead16(u32 addr)
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{
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u32 ret;
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CodeRegion = NDS::ARM7Read16(addr, &ret);
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return ret;
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}
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u32 CodeRead32(u32 addr)
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{
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u32 ret;
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CodeRegion = NDS::ARM7Read32(addr, &ret);
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return ret;
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}
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bool DataRead8(u32 addr, u32* val, u32 flags)
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{
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DataRegion = NDS::ARM7Read8(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM7MemTimings[DataRegion][0];
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else
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DataCycles += NDS::ARM7MemTimings[DataRegion][1];
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return true;
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}
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bool DataRead16(u32 addr, u32* val, u32 flags)
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{
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addr &= ~1;
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DataRegion = NDS::ARM7Read16(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM7MemTimings[DataRegion][0];
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else
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DataCycles += NDS::ARM7MemTimings[DataRegion][1];
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return true;
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}
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bool DataRead32(u32 addr, u32* val, u32 flags)
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{
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addr &= ~3;
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DataRegion = NDS::ARM7Read32(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM7MemTimings[DataRegion][2];
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else
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DataCycles += NDS::ARM7MemTimings[DataRegion][3];
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return true;
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}
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bool DataWrite8(u32 addr, u8 val, u32 flags)
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{
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DataRegion = NDS::ARM7Write8(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM7MemTimings[DataRegion][0];
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else
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DataCycles += NDS::ARM7MemTimings[DataRegion][1];
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return true;
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}
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bool DataWrite16(u32 addr, u16 val, u32 flags)
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{
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addr &= ~1;
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DataRegion = NDS::ARM7Write16(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM7MemTimings[DataRegion][0];
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else
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DataCycles += NDS::ARM7MemTimings[DataRegion][1];
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return true;
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}
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bool DataWrite32(u32 addr, u32 val, u32 flags)
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{
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addr &= ~3;
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DataRegion = NDS::ARM7Write32(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM7MemTimings[DataRegion][2];
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else
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DataCycles += NDS::ARM7MemTimings[DataRegion][3];
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return true;
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}
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void AddCycles_C()
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{
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// code only. this code fetch is sequential.
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Cycles += NDS::ARM7MemTimings[CodeRegion][(CPSR&0x20)?1:3];
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}
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void AddCycles_CI(s32 num)
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{
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// code+internal. results in a nonseq code fetch.
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Cycles += NDS::ARM7MemTimings[CodeRegion][(CPSR&0x20)?0:2] + num;
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}
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void AddCycles_CDI()
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{
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// LDR/LDM cycles.
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s32 numC = NDS::ARM7MemTimings[CodeRegion][(CPSR&0x20)?0:2];
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s32 numD = DataCycles;
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if (DataRegion == NDS::Region7_MainRAM)
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{
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if (CodeRegion == NDS::Region7_MainRAM)
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Cycles += numC + numD;
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else
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{
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numC++;
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Cycles += std::max(numC + numD - 3, std::max(numC, numD));
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}
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}
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else if (CodeRegion == NDS::Region7_MainRAM)
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{
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numD++;
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Cycles += std::max(numC + numD - 3, std::max(numC, numD));
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}
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else
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{
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Cycles += numC + numD + 1;
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}
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}
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void AddCycles_CD()
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{
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// TODO: max gain should be 5c when writing to mainRAM
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s32 numC = NDS::ARM7MemTimings[CodeRegion][(CPSR&0x20)?0:2];
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s32 numD = DataCycles;
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if (DataRegion == NDS::Region7_MainRAM)
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{
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if (CodeRegion == NDS::Region7_MainRAM)
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Cycles += numC + numD;
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else
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Cycles += std::max(numC + numD - 3, std::max(numC, numD));
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}
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else if (CodeRegion == NDS::Region7_MainRAM)
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{
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Cycles += std::max(numC + numD - 3, std::max(numC, numD));
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}
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else
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{
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Cycles += numC + numD;
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}
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}
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};
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namespace ARMInterpreter
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{
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