mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-22 05:40:15 -06:00
Cart refactor (#1073)
complete cart-interface refactor, will make this code a lot easier to deal with
This commit is contained in:
Arisotura
648
src/NDS.cpp
648
src/NDS.cpp
@ -1943,19 +1943,12 @@ u8 ARM9Read8(u32 addr)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return *(u8*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)];
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}
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return 0xFF; // TODO: proper open bus
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if (addr & 0x1) return GBACart::ROMRead(addr-1) >> 8;
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return GBACart::ROMRead(addr) & 0xFF;
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return GBACart_SRAM::Read8(addr & (GBACart_SRAM::SRAMLength-1));
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}
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return 0xFF; // TODO: proper open bus
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return GBACart::SRAMRead(addr);
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}
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printf("unknown arm9 read8 %08X\n", addr);
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@ -2008,22 +2001,15 @@ u16 ARM9Read16(u32 addr)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return 0x0000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return *(u16*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)];
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}
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return 0xFFFF; // TODO: proper open bus
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return GBACart::ROMRead(addr);
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return 0x0000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return GBACart_SRAM::Read16(addr & (GBACart_SRAM::SRAMLength-1));
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}
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return 0xFFFF; // TODO: proper open bus
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8);
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}
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//printf("unknown arm9 read16 %08X %08X\n", addr, ARM9->R[15]);
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if (addr) printf("unknown arm9 read16 %08X %08X\n", addr, ARM9->R[15]);
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return 0;
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}
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@ -2073,19 +2059,15 @@ u32 ARM9Read32(u32 addr)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00000000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return *(u32*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)];
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}
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return 0xFFFFFFFF; // TODO: proper open bus
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return GBACart::ROMRead(addr) |
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(GBACart::ROMRead(addr+2) << 16);
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00000000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return GBACart_SRAM::Read32(addr & (GBACart_SRAM::SRAMLength-1));
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}
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return 0xFFFFFFFF; // TODO: proper open bus
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8) |
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(GBACart::SRAMRead(addr+2) << 16) |
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(GBACart::SRAMRead(addr+3) << 24);
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}
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printf("unknown arm9 read32 %08X | %08X %08X\n", addr, ARM9->R[15], ARM9->R[12]);
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@ -2120,28 +2102,15 @@ void ARM9Write8(u32 addr, u8 val)
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case 0x05000000:
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case 0x06000000:
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case 0x07000000:
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// checkme
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return;
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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if ((addr & 0x00FFFFFF) >= 0xC4 && (addr & 0x00FFFFFF) <= 0xC9)
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{
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GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val);
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return;
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}
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}
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break;
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return;
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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GBACart_SRAM::Write8(addr & (GBACart_SRAM::SRAMLength-1), val);
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}
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GBACart::SRAMWrite(addr, val);
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return;
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}
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@ -2199,28 +2168,17 @@ void ARM9Write16(u32 addr, u16 val)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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// Note: the lower bound is adjusted such that a write starting
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// there will hit the first byte of the GPIO region.
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if ((addr & 0x00FFFFFF) >= 0xC3 && (addr & 0x00FFFFFF) <= 0xC9)
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{
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GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val);
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return;
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}
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}
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break;
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GBACart::ROMWrite(addr, val);
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return;
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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GBACart_SRAM::Write16(addr & (GBACart_SRAM::SRAMLength-1), val);
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}
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, val >> 8);
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return;
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}
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//printf("unknown arm9 write16 %08X %04X\n", addr, val);
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if (addr) printf("unknown arm9 write16 %08X %04X\n", addr, val);
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}
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void ARM9Write32(u32 addr, u32 val)
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@ -2274,29 +2232,20 @@ void ARM9Write32(u32 addr, u32 val)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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// Note: the lower bound is adjusted such that a write starting
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// there will hit the first byte of the GPIO region.
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if ((addr & 0x00FFFFFF) >= 0xC1 && (addr & 0x00FFFFFF) <= 0xC9)
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{
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GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val & 0xFF);
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GBACart::WriteGPIO((addr + 2) & (GBACart::CartROMSize-1), (val >> 16) & 0xFF);
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return;
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}
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}
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break;
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GBACart::ROMWrite(addr, val & 0xFFFF);
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GBACart::ROMWrite(addr+2, val >> 16);
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return;
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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GBACart_SRAM::Write32(addr & (GBACart_SRAM::SRAMLength-1), val);
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}
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, (val >> 8) & 0xFF);
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GBACart::SRAMWrite(addr+2, (val >> 16) & 0xFF);
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GBACart::SRAMWrite(addr+3, val >> 24);
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return;
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}
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//printf("unknown arm9 write32 %08X %08X | %08X\n", addr, val, ARM9->R[15]);
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printf("unknown arm9 write32 %08X %08X | %08X\n", addr, val, ARM9->R[15]);
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}
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bool ARM9GetMemRegion(u32 addr, bool write, MemRegion* region)
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@ -2366,26 +2315,30 @@ u8 ARM7Read8(u32 addr)
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case 0x04000000:
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return ARM7IORead8(addr);
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case 0x04800000:
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if (addr < 0x04810000)
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{
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if (addr & 0x1) return Wifi::Read(addr-1) >> 8;
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return Wifi::Read(addr) & 0xFF;
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}
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break;
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case 0x06000000:
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case 0x06800000:
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return GPU::ReadVRAM_ARM7<u8>(addr);
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case 0x08000000:
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case 0x08800000:
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return *(u8*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)];
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}
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return 0xFF; // TODO: proper open bus
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if (addr & 0x1) return GBACart::ROMRead(addr-1) >> 8;
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return GBACart::ROMRead(addr) & 0xFF;
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return GBACart_SRAM::Read8(addr & (GBACart_SRAM::SRAMLength-1));
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}
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return 0xFF; // TODO: proper open bus
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return GBACart::SRAMRead(addr);
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}
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printf("unknown arm7 read8 %08X %08X %08X/%08X\n", addr, ARM7->R[15], ARM7->R[0], ARM7->R[1]);
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@ -2438,21 +2391,17 @@ u16 ARM7Read16(u32 addr)
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return GPU::ReadVRAM_ARM7<u16>(addr);
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case 0x08000000:
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case 0x08800000:
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x0000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return *(u16*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)];
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}
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return 0xFFFF; // TODO: proper open bus
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return GBACart::ROMRead(addr);
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x0000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return GBACart_SRAM::Read16(addr & (GBACart_SRAM::SRAMLength-1));
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}
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return 0xFFFF; // TODO: proper open bus
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8);
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}
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printf("unknown arm7 read16 %08X %08X\n", addr, ARM7->R[15]);
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@ -2505,21 +2454,20 @@ u32 ARM7Read32(u32 addr)
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return GPU::ReadVRAM_ARM7<u32>(addr);
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case 0x08000000:
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case 0x08800000:
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00000000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return *(u32*)&GBACart::CartROM[addr & (GBACart::CartROMSize-1)];
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}
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return 0xFFFFFFFF; // TODO: proper open bus
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return GBACart::ROMRead(addr) |
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(GBACart::ROMRead(addr+2) << 16);
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00000000; // deselected CPU is 00h-filled
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if (GBACart::CartInserted)
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{
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return GBACart_SRAM::Read32(addr & (GBACart_SRAM::SRAMLength-1));
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}
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return 0xFFFFFFFF; // TODO: proper open bus
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8) |
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(GBACart::SRAMRead(addr+2) << 16) |
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(GBACart::SRAMRead(addr+3) << 24);
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}
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printf("unknown arm7 read32 %08X | %08X\n", addr, ARM7->R[15]);
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@ -2576,24 +2524,15 @@ void ARM7Write8(u32 addr, u8 val)
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return;
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case 0x08000000:
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case 0x08800000:
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case 0x09000000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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if ((addr & 0x00FFFFFF) >= 0xC4 && (addr & 0x00FFFFFF) <= 0xC9)
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{
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GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val);
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return;
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}
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}
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break;
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case 0x09800000:
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return;
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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GBACart_SRAM::Write8(addr & (GBACart_SRAM::SRAMLength-1), val);
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}
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GBACart::SRAMWrite(addr, val);
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return;
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}
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@ -2659,30 +2598,22 @@ void ARM7Write16(u32 addr, u16 val)
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return;
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case 0x08000000:
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case 0x08800000:
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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// Note: the lower bound is adjusted such that a write starting
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// there will hit the first byte of the GPIO region.
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if ((addr & 0x00FFFFFF) >= 0xC3 && (addr & 0x00FFFFFF) <= 0xC9)
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{
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GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val);
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return;
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}
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}
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break;
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GBACart::ROMWrite(addr, val);
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return;
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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GBACart_SRAM::Write16(addr & (GBACart_SRAM::SRAMLength-1), val);
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}
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, val >> 8);
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return;
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}
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//printf("unknown arm7 write16 %08X %04X @ %08X\n", addr, val, ARM7->R[15]);
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printf("unknown arm7 write16 %08X %04X @ %08X\n", addr, val, ARM7->R[15]);
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}
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void ARM7Write32(u32 addr, u32 val)
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@ -2744,31 +2675,25 @@ void ARM7Write32(u32 addr, u32 val)
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return;
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case 0x08000000:
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case 0x08800000:
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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// Note: the lower bound is adjusted such that a write starting
|
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// there will hit the first byte of the GPIO region.
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if ((addr & 0x00FFFFFF) >= 0xC1 && (addr & 0x00FFFFFF) <= 0xC9)
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{
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GBACart::WriteGPIO(addr & (GBACart::CartROMSize-1), val & 0xFF);
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GBACart::WriteGPIO((addr + 2) & (GBACart::CartROMSize-1), (val >> 16) & 0xFF);
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return;
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}
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}
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break;
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GBACart::ROMWrite(addr, val & 0xFFFF);
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GBACart::ROMWrite(addr+2, val >> 16);
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return;
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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if (GBACart::CartInserted)
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{
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GBACart_SRAM::Write32(addr & (GBACart_SRAM::SRAMLength-1), val);
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}
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, (val >> 8) & 0xFF);
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GBACart::SRAMWrite(addr+2, (val >> 16) & 0xFF);
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GBACart::SRAMWrite(addr+3, val >> 24);
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return;
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}
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//printf("unknown arm7 write32 %08X %08X @ %08X\n", addr, val, ARM7->R[15]);
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printf("unknown arm7 write32 %08X %08X @ %08X\n", addr, val, ARM7->R[15]);
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}
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bool ARM7GetMemRegion(u32 addr, bool write, MemRegion* region)
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@ -2838,16 +2763,43 @@ u8 ARM9IORead8(u32 addr)
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case 0x04000132: return KeyCnt & 0xFF;
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case 0x04000133: return KeyCnt >> 8;
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case 0x040001A2: return NDSCart::ReadSPIData();
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case 0x040001A2:
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if (!(ExMemCnt[0] & (1<<11)))
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return NDSCart::ReadSPIData();
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return 0;
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case 0x040001A8: return NDSCart::ROMCommand[0];
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case 0x040001A9: return NDSCart::ROMCommand[1];
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case 0x040001AA: return NDSCart::ROMCommand[2];
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case 0x040001AB: return NDSCart::ROMCommand[3];
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case 0x040001AC: return NDSCart::ROMCommand[4];
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case 0x040001AD: return NDSCart::ROMCommand[5];
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case 0x040001AE: return NDSCart::ROMCommand[6];
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case 0x040001AF: return NDSCart::ROMCommand[7];
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case 0x040001A8:
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if (!(ExMemCnt[0] & (1<<11)))
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return NDSCart::ROMCommand[0];
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return 0;
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case 0x040001A9:
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if (!(ExMemCnt[0] & (1<<11)))
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return NDSCart::ROMCommand[1];
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return 0;
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case 0x040001AA:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[2];
|
||||
return 0;
|
||||
case 0x040001AB:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[3];
|
||||
return 0;
|
||||
case 0x040001AC:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[4];
|
||||
return 0;
|
||||
case 0x040001AD:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[5];
|
||||
return 0;
|
||||
case 0x040001AE:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[6];
|
||||
return 0;
|
||||
case 0x040001AF:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[7];
|
||||
return 0;
|
||||
|
||||
case 0x04000208: return IME[0];
|
||||
|
||||
@ -2949,17 +2901,35 @@ u16 ARM9IORead16(u32 addr)
|
||||
return val;
|
||||
}
|
||||
|
||||
case 0x040001A0: return NDSCart::SPICnt;
|
||||
case 0x040001A2: return NDSCart::ReadSPIData();
|
||||
case 0x040001A0:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::SPICnt;
|
||||
return 0;
|
||||
case 0x040001A2:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ReadSPIData();
|
||||
return 0;
|
||||
|
||||
case 0x040001A8: return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8);
|
||||
case 0x040001AA: return NDSCart::ROMCommand[2] |
|
||||
(NDSCart::ROMCommand[3] << 8);
|
||||
case 0x040001AC: return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8);
|
||||
case 0x040001AE: return NDSCart::ROMCommand[6] |
|
||||
(NDSCart::ROMCommand[7] << 8);
|
||||
case 0x040001A8:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8);
|
||||
return 0;
|
||||
case 0x040001AA:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[2] |
|
||||
(NDSCart::ROMCommand[3] << 8);
|
||||
return 0;
|
||||
case 0x040001AC:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8);
|
||||
return 0;
|
||||
case 0x040001AE:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[6] |
|
||||
(NDSCart::ROMCommand[7] << 8);
|
||||
return 0;
|
||||
|
||||
case 0x04000204: return ExMemCnt[0];
|
||||
case 0x04000208: return IME[0];
|
||||
@ -3058,17 +3028,29 @@ u32 ARM9IORead32(u32 addr)
|
||||
case 0x04000180: return IPCSync9;
|
||||
case 0x04000184: return ARM9IORead16(addr);
|
||||
|
||||
case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
|
||||
case 0x040001A4: return NDSCart::ROMCnt;
|
||||
case 0x040001A0:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
|
||||
return 0;
|
||||
case 0x040001A4:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCnt;
|
||||
return 0;
|
||||
|
||||
case 0x040001A8: return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8) |
|
||||
(NDSCart::ROMCommand[2] << 16) |
|
||||
(NDSCart::ROMCommand[3] << 24);
|
||||
case 0x040001AC: return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8) |
|
||||
(NDSCart::ROMCommand[6] << 16) |
|
||||
(NDSCart::ROMCommand[7] << 24);
|
||||
case 0x040001A8:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8) |
|
||||
(NDSCart::ROMCommand[2] << 16) |
|
||||
(NDSCart::ROMCommand[3] << 24);
|
||||
return 0;
|
||||
case 0x040001AC:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8) |
|
||||
(NDSCart::ROMCommand[6] << 16) |
|
||||
(NDSCart::ROMCommand[7] << 24);
|
||||
return 0;
|
||||
|
||||
case 0x04000208: return IME[0];
|
||||
case 0x04000210: return IE[0];
|
||||
@ -3155,34 +3137,31 @@ void ARM9IOWrite8(u32 addr, u8 val)
|
||||
KeyCnt = (KeyCnt & 0x00FF) | (val << 8);
|
||||
return;
|
||||
|
||||
case 0x040001A0:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::WriteSPICnt((NDSCart::SPICnt & 0xFF00) | val);
|
||||
}
|
||||
return;
|
||||
case 0x040001A1:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::WriteSPICnt((NDSCart::SPICnt & 0x00FF) | (val << 8));
|
||||
}
|
||||
return;
|
||||
case 0x040001A2:
|
||||
NDSCart::WriteSPIData(val);
|
||||
return;
|
||||
|
||||
case 0x04000188:
|
||||
ARM9IOWrite32(addr, val | (val << 8) | (val << 16) | (val << 24));
|
||||
return;
|
||||
|
||||
case 0x040001A8: NDSCart::ROMCommand[0] = val; return;
|
||||
case 0x040001A9: NDSCart::ROMCommand[1] = val; return;
|
||||
case 0x040001AA: NDSCart::ROMCommand[2] = val; return;
|
||||
case 0x040001AB: NDSCart::ROMCommand[3] = val; return;
|
||||
case 0x040001AC: NDSCart::ROMCommand[4] = val; return;
|
||||
case 0x040001AD: NDSCart::ROMCommand[5] = val; return;
|
||||
case 0x040001AE: NDSCart::ROMCommand[6] = val; return;
|
||||
case 0x040001AF: NDSCart::ROMCommand[7] = val; return;
|
||||
case 0x040001A0:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
NDSCart::WriteSPICnt((NDSCart::SPICnt & 0xFF00) | val);
|
||||
return;
|
||||
case 0x040001A1:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
NDSCart::WriteSPICnt((NDSCart::SPICnt & 0x00FF) | (val << 8));
|
||||
return;
|
||||
case 0x040001A2:
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
NDSCart::WriteSPIData(val);
|
||||
return;
|
||||
|
||||
case 0x040001A8: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[0] = val; return;
|
||||
case 0x040001A9: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[1] = val; return;
|
||||
case 0x040001AA: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[2] = val; return;
|
||||
case 0x040001AB: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[3] = val; return;
|
||||
case 0x040001AC: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[4] = val; return;
|
||||
case 0x040001AD: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[5] = val; return;
|
||||
case 0x040001AE: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[6] = val; return;
|
||||
case 0x040001AF: if (!(ExMemCnt[0] & (1<<11))) NDSCart::ROMCommand[7] = val; return;
|
||||
|
||||
case 0x04000208: IME[0] = val & 0x1; UpdateIRQ(0); return;
|
||||
|
||||
@ -3296,27 +3275,41 @@ void ARM9IOWrite16(u32 addr, u16 val)
|
||||
return;
|
||||
|
||||
case 0x040001A0:
|
||||
if (!(ExMemCnt[0] & (1<<11))) NDSCart::WriteSPICnt(val);
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
NDSCart::WriteSPICnt(val);
|
||||
return;
|
||||
case 0x040001A2:
|
||||
NDSCart::WriteSPIData(val & 0xFF);
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
NDSCart::WriteSPIData(val & 0xFF);
|
||||
return;
|
||||
|
||||
case 0x040001A8:
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = val >> 8;
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = val >> 8;
|
||||
}
|
||||
return;
|
||||
case 0x040001AA:
|
||||
NDSCart::ROMCommand[2] = val & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 8;
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::ROMCommand[2] = val & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 8;
|
||||
}
|
||||
return;
|
||||
case 0x040001AC:
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = val >> 8;
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = val >> 8;
|
||||
}
|
||||
return;
|
||||
case 0x040001AE:
|
||||
NDSCart::ROMCommand[6] = val & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 8;
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::ROMCommand[6] = val & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 8;
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x040001B8: ROMSeed0[4] = val & 0x7F; return;
|
||||
@ -3470,20 +3463,27 @@ void ARM9IOWrite32(u32 addr, u32 val)
|
||||
}
|
||||
return;
|
||||
case 0x040001A4:
|
||||
if (!(ExMemCnt[0] & (1<<11))) NDSCart::WriteROMCnt(val);
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
NDSCart::WriteROMCnt(val);
|
||||
return;
|
||||
|
||||
case 0x040001A8:
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[2] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 24;
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[2] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 24;
|
||||
}
|
||||
return;
|
||||
case 0x040001AC:
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[6] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 24;
|
||||
if (!(ExMemCnt[0] & (1<<11)))
|
||||
{
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[6] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 24;
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x040001B0: *(u32*)&ROMSeed0[0] = val; return;
|
||||
@ -3528,7 +3528,7 @@ void ARM9IOWrite32(u32 addr, u32 val)
|
||||
return;
|
||||
|
||||
case 0x04100010:
|
||||
NDSCart::WriteROMData(val);
|
||||
if (!(ExMemCnt[0] & (1<<11))) NDSCart::WriteROMData(val);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -3567,16 +3567,43 @@ u8 ARM7IORead8(u32 addr)
|
||||
|
||||
case 0x04000138: return RTC::Read() & 0xFF;
|
||||
|
||||
case 0x040001A2: return NDSCart::ReadSPIData();
|
||||
case 0x040001A2:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ReadSPIData();
|
||||
return 0;
|
||||
|
||||
case 0x040001A8: return NDSCart::ROMCommand[0];
|
||||
case 0x040001A9: return NDSCart::ROMCommand[1];
|
||||
case 0x040001AA: return NDSCart::ROMCommand[2];
|
||||
case 0x040001AB: return NDSCart::ROMCommand[3];
|
||||
case 0x040001AC: return NDSCart::ROMCommand[4];
|
||||
case 0x040001AD: return NDSCart::ROMCommand[5];
|
||||
case 0x040001AE: return NDSCart::ROMCommand[6];
|
||||
case 0x040001AF: return NDSCart::ROMCommand[7];
|
||||
case 0x040001A8:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[0];
|
||||
return 0;
|
||||
case 0x040001A9:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[1];
|
||||
return 0;
|
||||
case 0x040001AA:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[2];
|
||||
return 0;
|
||||
case 0x040001AB:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[3];
|
||||
return 0;
|
||||
case 0x040001AC:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[4];
|
||||
return 0;
|
||||
case 0x040001AD:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[5];
|
||||
return 0;
|
||||
case 0x040001AE:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[6];
|
||||
return 0;
|
||||
case 0x040001AF:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[7];
|
||||
return 0;
|
||||
|
||||
case 0x040001C2: return SPI::ReadData();
|
||||
|
||||
@ -3640,17 +3667,29 @@ u16 ARM7IORead16(u32 addr)
|
||||
return val;
|
||||
}
|
||||
|
||||
case 0x040001A0: return NDSCart::SPICnt;
|
||||
case 0x040001A2: return NDSCart::ReadSPIData();
|
||||
case 0x040001A0: if (ExMemCnt[0] & (1<<11)) return NDSCart::SPICnt; return 0;
|
||||
case 0x040001A2: if (ExMemCnt[0] & (1<<11)) return NDSCart::ReadSPIData(); return 0;
|
||||
|
||||
case 0x040001A8: return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8);
|
||||
case 0x040001AA: return NDSCart::ROMCommand[2] |
|
||||
(NDSCart::ROMCommand[3] << 8);
|
||||
case 0x040001AC: return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8);
|
||||
case 0x040001AE: return NDSCart::ROMCommand[6] |
|
||||
(NDSCart::ROMCommand[7] << 8);
|
||||
case 0x040001A8:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8);
|
||||
return 0;
|
||||
case 0x040001AA:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[2] |
|
||||
(NDSCart::ROMCommand[3] << 8);
|
||||
return 0;
|
||||
case 0x040001AC:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8);
|
||||
return 0;
|
||||
case 0x040001AE:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[6] |
|
||||
(NDSCart::ROMCommand[7] << 8);
|
||||
return 0;
|
||||
|
||||
case 0x040001C0: return SPI::Cnt;
|
||||
case 0x040001C2: return SPI::ReadData();
|
||||
@ -3707,17 +3746,29 @@ u32 ARM7IORead32(u32 addr)
|
||||
case 0x04000180: return IPCSync7;
|
||||
case 0x04000184: return ARM7IORead16(addr);
|
||||
|
||||
case 0x040001A0: return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
|
||||
case 0x040001A4: return NDSCart::ROMCnt;
|
||||
case 0x040001A0:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::SPICnt | (NDSCart::ReadSPIData() << 16);
|
||||
return 0;
|
||||
case 0x040001A4:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCnt;
|
||||
return 0;
|
||||
|
||||
case 0x040001A8: return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8) |
|
||||
(NDSCart::ROMCommand[2] << 16) |
|
||||
(NDSCart::ROMCommand[3] << 24);
|
||||
case 0x040001AC: return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8) |
|
||||
(NDSCart::ROMCommand[6] << 16) |
|
||||
(NDSCart::ROMCommand[7] << 24);
|
||||
case 0x040001A8:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[0] |
|
||||
(NDSCart::ROMCommand[1] << 8) |
|
||||
(NDSCart::ROMCommand[2] << 16) |
|
||||
(NDSCart::ROMCommand[3] << 24);
|
||||
return 0;
|
||||
case 0x040001AC:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
return NDSCart::ROMCommand[4] |
|
||||
(NDSCart::ROMCommand[5] << 8) |
|
||||
(NDSCart::ROMCommand[6] << 16) |
|
||||
(NDSCart::ROMCommand[7] << 24);
|
||||
return 0;
|
||||
|
||||
case 0x040001C0:
|
||||
return SPI::Cnt | (SPI::ReadData() << 16);
|
||||
@ -3794,22 +3845,21 @@ void ARM7IOWrite8(u32 addr, u8 val)
|
||||
return;
|
||||
case 0x040001A1:
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
{
|
||||
NDSCart::WriteSPICnt((NDSCart::SPICnt & 0x00FF) | (val << 8));
|
||||
}
|
||||
return;
|
||||
case 0x040001A2:
|
||||
NDSCart::WriteSPIData(val);
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
NDSCart::WriteSPIData(val);
|
||||
return;
|
||||
|
||||
case 0x040001A8: NDSCart::ROMCommand[0] = val; return;
|
||||
case 0x040001A9: NDSCart::ROMCommand[1] = val; return;
|
||||
case 0x040001AA: NDSCart::ROMCommand[2] = val; return;
|
||||
case 0x040001AB: NDSCart::ROMCommand[3] = val; return;
|
||||
case 0x040001AC: NDSCart::ROMCommand[4] = val; return;
|
||||
case 0x040001AD: NDSCart::ROMCommand[5] = val; return;
|
||||
case 0x040001AE: NDSCart::ROMCommand[6] = val; return;
|
||||
case 0x040001AF: NDSCart::ROMCommand[7] = val; return;
|
||||
case 0x040001A8: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[0] = val; return;
|
||||
case 0x040001A9: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[1] = val; return;
|
||||
case 0x040001AA: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[2] = val; return;
|
||||
case 0x040001AB: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[3] = val; return;
|
||||
case 0x040001AC: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[4] = val; return;
|
||||
case 0x040001AD: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[5] = val; return;
|
||||
case 0x040001AE: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[6] = val; return;
|
||||
case 0x040001AF: if (ExMemCnt[0] & (1<<11)) NDSCart::ROMCommand[7] = val; return;
|
||||
|
||||
case 0x040001C2:
|
||||
SPI::WriteData(val);
|
||||
@ -3903,24 +3953,37 @@ void ARM7IOWrite16(u32 addr, u16 val)
|
||||
NDSCart::WriteSPICnt(val);
|
||||
return;
|
||||
case 0x040001A2:
|
||||
NDSCart::WriteSPIData(val & 0xFF);
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
NDSCart::WriteSPIData(val & 0xFF);
|
||||
return;
|
||||
|
||||
case 0x040001A8:
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = val >> 8;
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
{
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = val >> 8;
|
||||
}
|
||||
return;
|
||||
case 0x040001AA:
|
||||
NDSCart::ROMCommand[2] = val & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 8;
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
{
|
||||
NDSCart::ROMCommand[2] = val & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 8;
|
||||
}
|
||||
return;
|
||||
case 0x040001AC:
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = val >> 8;
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
{
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = val >> 8;
|
||||
}
|
||||
return;
|
||||
case 0x040001AE:
|
||||
NDSCart::ROMCommand[6] = val & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 8;
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
{
|
||||
NDSCart::ROMCommand[6] = val & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 8;
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x040001B8: ROMSeed0[12] = val & 0x7F; return;
|
||||
@ -4040,20 +4103,27 @@ void ARM7IOWrite32(u32 addr, u32 val)
|
||||
}
|
||||
return;
|
||||
case 0x040001A4:
|
||||
if (ExMemCnt[0] & (1<<11)) NDSCart::WriteROMCnt(val);
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
NDSCart::WriteROMCnt(val);
|
||||
return;
|
||||
|
||||
case 0x040001A8:
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[2] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 24;
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
{
|
||||
NDSCart::ROMCommand[0] = val & 0xFF;
|
||||
NDSCart::ROMCommand[1] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[2] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[3] = val >> 24;
|
||||
}
|
||||
return;
|
||||
case 0x040001AC:
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[6] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 24;
|
||||
if (ExMemCnt[0] & (1<<11))
|
||||
{
|
||||
NDSCart::ROMCommand[4] = val & 0xFF;
|
||||
NDSCart::ROMCommand[5] = (val >> 8) & 0xFF;
|
||||
NDSCart::ROMCommand[6] = (val >> 16) & 0xFF;
|
||||
NDSCart::ROMCommand[7] = val >> 24;
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x040001B0: *(u32*)&ROMSeed0[8] = val; return;
|
||||
@ -4074,6 +4144,10 @@ void ARM7IOWrite32(u32 addr, u32 val)
|
||||
if (ARM7BIOSProt == 0)
|
||||
ARM7BIOSProt = val & 0xFFFE;
|
||||
return;
|
||||
|
||||
case 0x04100010:
|
||||
if (ExMemCnt[0] & (1<<11)) NDSCart::WriteROMData(val);
|
||||
return;
|
||||
}
|
||||
|
||||
if (addr >= 0x04000400 && addr < 0x04000520)
|
||||
|
||||
Reference in New Issue
Block a user