mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-21 13:20:57 -06:00
having fun with fatfs (#1189)
* patch TSC coords in DSi mode * DSiware importer and shit
This commit is contained in:
Arisotura
282
src/DSi.cpp
282
src/DSi.cpp
@ -36,6 +36,7 @@
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#include "DSi_I2C.h"
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#include "DSi_SD.h"
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#include "DSi_AES.h"
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#include "DSi_NAND.h"
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#include "DSi_DSP.h"
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#include "DSi_Camera.h"
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@ -348,6 +349,12 @@ bool LoadNAND()
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{
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printf("Loading DSi NAND\n");
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if (!DSi_NAND::Init(SDMMCFile, &DSi::ARM7iBIOS[0x8308]))
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{
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printf("Failed to load DSi NAND\n");
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return false;
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}
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// Make sure NWRAM is accessible.
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// The Bits are set to the startup values in Reset() and we might
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// still have them on default (0) or some bits cleared by the previous
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@ -367,155 +374,130 @@ bool LoadNAND()
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memset(NWRAMEnd, 0, sizeof(NWRAMEnd));
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memset(NWRAMMask, 0, sizeof(NWRAMMask));
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if (SDMMCFile)
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u32 bootparams[8];
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fseek(SDMMCFile, 0x220, SEEK_SET);
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fread(bootparams, 4, 8, SDMMCFile);
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printf("ARM9: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
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bootparams[0], bootparams[1], bootparams[2], bootparams[3]);
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printf("ARM7: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
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bootparams[4], bootparams[5], bootparams[6], bootparams[7]);
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// read and apply new-WRAM settings
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MBK[0][8] = 0;
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MBK[1][8] = 0;
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u32 mbk[12];
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fseek(SDMMCFile, 0x380, SEEK_SET);
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fread(mbk, 4, 12, SDMMCFile);
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MapNWRAM_A(0, mbk[0] & 0xFF);
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MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
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MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
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MapNWRAM_A(3, mbk[0] >> 24);
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MapNWRAM_B(0, mbk[1] & 0xFF);
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MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
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MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
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MapNWRAM_B(3, mbk[1] >> 24);
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MapNWRAM_B(4, mbk[2] & 0xFF);
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MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
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MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
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MapNWRAM_B(7, mbk[2] >> 24);
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MapNWRAM_C(0, mbk[3] & 0xFF);
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MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
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MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
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MapNWRAM_C(3, mbk[3] >> 24);
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MapNWRAM_C(4, mbk[4] & 0xFF);
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MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
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MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
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MapNWRAM_C(7, mbk[4] >> 24);
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MapNWRAMRange(0, 0, mbk[5]);
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MapNWRAMRange(0, 1, mbk[6]);
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MapNWRAMRange(0, 2, mbk[7]);
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MapNWRAMRange(1, 0, mbk[8]);
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MapNWRAMRange(1, 1, mbk[9]);
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MapNWRAMRange(1, 2, mbk[10]);
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// TODO: find out why it is 0xFF000000
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mbk[11] &= 0x00FFFF0F;
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MBK[0][8] = mbk[11];
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MBK[1][8] = mbk[11];
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// load boot2 binaries
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AES_ctx ctx;
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const u8 boot2key[16] = {0xAD, 0x34, 0xEC, 0xF9, 0x62, 0x6E, 0xC2, 0x3A, 0xF6, 0xB4, 0x6C, 0x00, 0x80, 0x80, 0xEE, 0x98};
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u8 boot2iv[16];
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u8 tmp[16];
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u32 dstaddr;
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*(u32*)&tmp[0] = bootparams[3];
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*(u32*)&tmp[4] = -bootparams[3];
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*(u32*)&tmp[8] = ~bootparams[3];
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*(u32*)&tmp[12] = 0;
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for (int i = 0; i < 16; i++) boot2iv[i] = tmp[15-i];
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AES_init_ctx_iv(&ctx, boot2key, boot2iv);
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fseek(SDMMCFile, bootparams[0], SEEK_SET);
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dstaddr = bootparams[2];
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for (u32 i = 0; i < bootparams[3]; i += 16)
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{
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u32 bootparams[8];
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fseek(SDMMCFile, 0x220, SEEK_SET);
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fread(bootparams, 4, 8, SDMMCFile);
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u8 data[16];
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fread(data, 16, 1, SDMMCFile);
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printf("ARM9: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
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bootparams[0], bootparams[1], bootparams[2], bootparams[3]);
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printf("ARM7: offset=%08X size=%08X RAM=%08X size_aligned=%08X\n",
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bootparams[4], bootparams[5], bootparams[6], bootparams[7]);
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for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
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AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
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for (int j = 0; j < 16; j++) data[j] = tmp[15-j];
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// read and apply new-WRAM settings
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ARM9Write32(dstaddr, *(u32*)&data[0]); dstaddr += 4;
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ARM9Write32(dstaddr, *(u32*)&data[4]); dstaddr += 4;
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ARM9Write32(dstaddr, *(u32*)&data[8]); dstaddr += 4;
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ARM9Write32(dstaddr, *(u32*)&data[12]); dstaddr += 4;
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}
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MBK[0][8] = 0;
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MBK[1][8] = 0;
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*(u32*)&tmp[0] = bootparams[7];
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*(u32*)&tmp[4] = -bootparams[7];
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*(u32*)&tmp[8] = ~bootparams[7];
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*(u32*)&tmp[12] = 0;
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for (int i = 0; i < 16; i++) boot2iv[i] = tmp[15-i];
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u32 mbk[12];
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fseek(SDMMCFile, 0x380, SEEK_SET);
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fread(mbk, 4, 12, SDMMCFile);
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AES_init_ctx_iv(&ctx, boot2key, boot2iv);
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MapNWRAM_A(0, mbk[0] & 0xFF);
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MapNWRAM_A(1, (mbk[0] >> 8) & 0xFF);
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MapNWRAM_A(2, (mbk[0] >> 16) & 0xFF);
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MapNWRAM_A(3, mbk[0] >> 24);
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fseek(SDMMCFile, bootparams[4], SEEK_SET);
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dstaddr = bootparams[6];
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for (u32 i = 0; i < bootparams[7]; i += 16)
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{
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u8 data[16];
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fread(data, 16, 1, SDMMCFile);
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MapNWRAM_B(0, mbk[1] & 0xFF);
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MapNWRAM_B(1, (mbk[1] >> 8) & 0xFF);
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MapNWRAM_B(2, (mbk[1] >> 16) & 0xFF);
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MapNWRAM_B(3, mbk[1] >> 24);
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MapNWRAM_B(4, mbk[2] & 0xFF);
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MapNWRAM_B(5, (mbk[2] >> 8) & 0xFF);
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MapNWRAM_B(6, (mbk[2] >> 16) & 0xFF);
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MapNWRAM_B(7, mbk[2] >> 24);
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for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
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AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
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for (int j = 0; j < 16; j++) data[j] = tmp[15-j];
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MapNWRAM_C(0, mbk[3] & 0xFF);
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MapNWRAM_C(1, (mbk[3] >> 8) & 0xFF);
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MapNWRAM_C(2, (mbk[3] >> 16) & 0xFF);
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MapNWRAM_C(3, mbk[3] >> 24);
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MapNWRAM_C(4, mbk[4] & 0xFF);
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MapNWRAM_C(5, (mbk[4] >> 8) & 0xFF);
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MapNWRAM_C(6, (mbk[4] >> 16) & 0xFF);
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MapNWRAM_C(7, mbk[4] >> 24);
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ARM7Write32(dstaddr, *(u32*)&data[0]); dstaddr += 4;
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ARM7Write32(dstaddr, *(u32*)&data[4]); dstaddr += 4;
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ARM7Write32(dstaddr, *(u32*)&data[8]); dstaddr += 4;
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ARM7Write32(dstaddr, *(u32*)&data[12]); dstaddr += 4;
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}
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MapNWRAMRange(0, 0, mbk[5]);
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MapNWRAMRange(0, 1, mbk[6]);
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MapNWRAMRange(0, 2, mbk[7]);
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// repoint the CPUs to the boot2 binaries
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MapNWRAMRange(1, 0, mbk[8]);
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MapNWRAMRange(1, 1, mbk[9]);
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MapNWRAMRange(1, 2, mbk[10]);
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// TODO: find out why it is 0xFF000000
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mbk[11] &= 0x00FFFF0F;
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MBK[0][8] = mbk[11];
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MBK[1][8] = mbk[11];
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// load boot2 binaries
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AES_ctx ctx;
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const u8 boot2key[16] = {0xAD, 0x34, 0xEC, 0xF9, 0x62, 0x6E, 0xC2, 0x3A, 0xF6, 0xB4, 0x6C, 0x00, 0x80, 0x80, 0xEE, 0x98};
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u8 boot2iv[16];
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u8 tmp[16];
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u32 dstaddr;
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*(u32*)&tmp[0] = bootparams[3];
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*(u32*)&tmp[4] = -bootparams[3];
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*(u32*)&tmp[8] = ~bootparams[3];
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*(u32*)&tmp[12] = 0;
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for (int i = 0; i < 16; i++) boot2iv[i] = tmp[15-i];
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AES_init_ctx_iv(&ctx, boot2key, boot2iv);
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fseek(SDMMCFile, bootparams[0], SEEK_SET);
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dstaddr = bootparams[2];
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for (u32 i = 0; i < bootparams[3]; i += 16)
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{
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u8 data[16];
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fread(data, 16, 1, SDMMCFile);
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for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
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AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
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for (int j = 0; j < 16; j++) data[j] = tmp[15-j];
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ARM9Write32(dstaddr, *(u32*)&data[0]); dstaddr += 4;
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ARM9Write32(dstaddr, *(u32*)&data[4]); dstaddr += 4;
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ARM9Write32(dstaddr, *(u32*)&data[8]); dstaddr += 4;
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ARM9Write32(dstaddr, *(u32*)&data[12]); dstaddr += 4;
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}
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*(u32*)&tmp[0] = bootparams[7];
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*(u32*)&tmp[4] = -bootparams[7];
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*(u32*)&tmp[8] = ~bootparams[7];
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*(u32*)&tmp[12] = 0;
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for (int i = 0; i < 16; i++) boot2iv[i] = tmp[15-i];
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AES_init_ctx_iv(&ctx, boot2key, boot2iv);
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fseek(SDMMCFile, bootparams[4], SEEK_SET);
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dstaddr = bootparams[6];
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for (u32 i = 0; i < bootparams[7]; i += 16)
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{
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u8 data[16];
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fread(data, 16, 1, SDMMCFile);
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for (int j = 0; j < 16; j++) tmp[j] = data[15-j];
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AES_CTR_xcrypt_buffer(&ctx, tmp, 16);
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for (int j = 0; j < 16; j++) data[j] = tmp[15-j];
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ARM7Write32(dstaddr, *(u32*)&data[0]); dstaddr += 4;
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ARM7Write32(dstaddr, *(u32*)&data[4]); dstaddr += 4;
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ARM7Write32(dstaddr, *(u32*)&data[8]); dstaddr += 4;
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ARM7Write32(dstaddr, *(u32*)&data[12]); dstaddr += 4;
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}
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// repoint the CPUs to the boot2 binaries
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BootAddr[0] = bootparams[2];
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BootAddr[1] = bootparams[6];
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BootAddr[0] = bootparams[2];
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BootAddr[1] = bootparams[6];
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#define printhex(str, size) { for (int z = 0; z < (size); z++) printf("%02X", (str)[z]); printf("\n"); }
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#define printhex_rev(str, size) { for (int z = (size)-1; z >= 0; z--) printf("%02X", (str)[z]); printf("\n"); }
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// read the nocash footer
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DSi_NAND::GetIDs(eMMC_CID, ConsoleID);
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fseek(SDMMCFile, -0x40, SEEK_END);
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char nand_footer[16];
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const char* nand_footer_ref = "DSi eMMC CID/CPU";
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fread(nand_footer, 1, 16, SDMMCFile);
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if (memcmp(nand_footer, nand_footer_ref, 16))
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{
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// There is another copy of the footer at 000FF800h for the case
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// that by external tools the image was cut off
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// See https://problemkaputt.de/gbatek.htm#dsisdmmcimages
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fseek(SDMMCFile, 0x000FF800, SEEK_SET);
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fread(nand_footer, 1, 16, SDMMCFile);
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if (memcmp(nand_footer, nand_footer_ref, 16))
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{
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printf("ERROR: NAND missing nocash footer\n");
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return false;
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}
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}
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fread(eMMC_CID, 1, 16, SDMMCFile);
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fread(&ConsoleID, 1, 8, SDMMCFile);
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printf("eMMC CID: "); printhex(eMMC_CID, 16);
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printf("Console ID: %" PRIx64 "\n", ConsoleID);
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}
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printf("eMMC CID: "); printhex(eMMC_CID, 16);
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printf("Console ID: %" PRIx64 "\n", ConsoleID);
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memset(ITCMInit, 0, 0x8000);
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memcpy(&ITCMInit[0x4400], &ARM9iBIOS[0x87F4], 0x400);
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@ -529,6 +511,10 @@ bool LoadNAND()
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memcpy(&ARM7Init[0x0254], &ARM7iBIOS[0xC6D0], 0x1048);
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memcpy(&ARM7Init[0x129C], &ARM7iBIOS[0xD718], 0x1048);
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DSi_NAND::PatchTSC();
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DSi_NAND::DeInit();
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return true;
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}
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@ -638,7 +624,7 @@ void MapNWRAM_A(u32 num, u8 val)
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// When we only update the mapping on the written MBK, we will
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// have priority of the last witten MBK over the others
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// However the hardware has a fixed order. Therefor
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// However the hardware has a fixed order. Therefor
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// we need to iterate through them all in a fixed order and update
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// the mapping, so the result is independend on the MBK write order
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for (unsigned int part = 0; part < 4; part++)
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@ -686,7 +672,7 @@ void MapNWRAM_B(u32 num, u8 val)
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// When we only update the mapping on the written MBK, we will
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// have priority of the last witten MBK over the others
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// However the hardware has a fixed order. Therefor
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// However the hardware has a fixed order. Therefor
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// we need to iterate through them all in a fixed order and update
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// the mapping, so the result is independend on the MBK write order
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for (unsigned int part = 0; part < 8; part++)
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@ -741,7 +727,7 @@ void MapNWRAM_C(u32 num, u8 val)
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// When we only update the mapping on the written MBK, we will
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// have priority of the last witten MBK over the others
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// However the hardware has a fixed order. Therefor
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// However the hardware has a fixed order. Therefor
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// we need to iterate through them all in a fixed order and update
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// the mapping, so the result is independend on the MBK write order
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for (unsigned int part = 0; part < 8; part++)
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@ -2139,17 +2125,17 @@ void ARM9IOWrite32(u32 addr, u32 val)
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MapNWRAM_C(6, (val >> 16) & 0xFF);
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MapNWRAM_C(7, val >> 24);
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return;
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case 0x04004054:
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case 0x04004054:
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if (!(SCFG_EXT[0] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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MapNWRAMRange(0, 0, val);
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return;
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case 0x04004058:
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case 0x04004058:
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if (!(SCFG_EXT[0] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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MapNWRAMRange(0, 1, val);
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MapNWRAMRange(0, 1, val);
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return;
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case 0x0400405C:
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case 0x0400405C:
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if (!(SCFG_EXT[0] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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MapNWRAMRange(0, 2, val);
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@ -2200,7 +2186,7 @@ u8 ARM7IORead8(u32 addr)
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{
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switch (addr)
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{
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case 0x04004000:
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case 0x04004000:
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return SCFG_BIOS & 0xFF;
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case 0x04004001: return SCFG_BIOS >> 8;
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@ -2456,27 +2442,27 @@ void ARM7IOWrite32(u32 addr, u32 val)
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Set_SCFG_MC(val);
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return;
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case 0x04004054:
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case 0x04004054:
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if (!(SCFG_EXT[1] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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MapNWRAMRange(1, 0, val);
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return;
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case 0x04004058:
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case 0x04004058:
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if (!(SCFG_EXT[1] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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MapNWRAMRange(1, 1, val);
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return;
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case 0x0400405C:
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case 0x0400405C:
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if (!(SCFG_EXT[1] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
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MapNWRAMRange(1, 2, val);
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return;
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case 0x04004060:
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case 0x04004060:
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if (!(SCFG_EXT[1] & (1 << 31))) /* no access to SCFG Registers if disabled*/
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return;
|
||||
val &= 0x00FFFF0F;
|
||||
MBK[0][8] = val;
|
||||
MBK[1][8] = val;
|
||||
MBK[0][8] = val;
|
||||
MBK[1][8] = val;
|
||||
return;
|
||||
|
||||
case 0x04004100: NDMACnt[1] = val & 0x800F0000; return;
|
||||
|
||||
Reference in New Issue
Block a user