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data abort handling for (almost) all (arm) instructions

Browse Source 
full list: strb, ldrb, strh, ldrd, strd, ldrh, ldrsb, ldrsh
This commit is contained in:
Jaklyy
2024-06-04 21:22:39 -04:00
parent 1e8194e367
commit 317a8c61e5
4 changed files with 102 additions and 80 deletions
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36
src/CP15.cpp
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@ -807,12 +807,12 @@ u32 ARMv5::CodeRead32(u32 addr, bool branch)
}
void ARMv5::DataRead8(u32 addr, u32* val)
bool ARMv5::DataRead8(u32 addr, u32* val)
{
if (!(PU_Map[addr>>12] & 0x01))
{
DataAbort();
return;
return false;
}
DataRegion = addr;
@ -821,25 +821,26 @@ void ARMv5::DataRead8(u32 addr, u32* val)
{
DataCycles = 1;
*val = *(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*val = *(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return;
return true;
}
*val = BusRead8(addr);
DataCycles = MemTimings[addr >> 12][1];
return true;
}
void ARMv5::DataRead16(u32 addr, u32* val)
bool ARMv5::DataRead16(u32 addr, u32* val)
{
if (!(PU_Map[addr>>12] & 0x01))
{
DataAbort();
return;
return false;
}
DataRegion = addr;
@ -850,17 +851,18 @@ void ARMv5::DataRead16(u32 addr, u32* val)
{
DataCycles = 1;
*val = *(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)];
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*val = *(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)];
return;
return true;
}
*val = BusRead16(addr);
DataCycles = MemTimings[addr >> 12][1];
return true;
}
bool ARMv5::DataRead32(u32 addr, u32* val)
@ -921,12 +923,12 @@ bool ARMv5::DataRead32S(u32 addr, u32* val)
return true;
}
void ARMv5::DataWrite8(u32 addr, u8 val)
bool ARMv5::DataWrite8(u32 addr, u8 val)
{
if (!(PU_Map[addr>>12] & 0x02))
{
DataAbort();
return;
return false;
}
DataRegion = addr;
@ -936,25 +938,26 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
DataCycles = 1;
*(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
return true;
}
BusWrite8(addr, val);
DataCycles = MemTimings[addr >> 12][1];
return true;
}
void ARMv5::DataWrite16(u32 addr, u16 val)
bool ARMv5::DataWrite16(u32 addr, u16 val)
{
if (!(PU_Map[addr>>12] & 0x02))
{
DataAbort();
return;
return false;
}
DataRegion = addr;
@ -966,17 +969,18 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
DataCycles = 1;
*(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
return;
return true;
}
if ((addr & DTCMMask) == DTCMBase)
{
DataCycles = 1;
*(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return;
return true;
}
BusWrite16(addr, val);
DataCycles = MemTimings[addr >> 12][1];
return true;
}
bool ARMv5::DataWrite32(u32 addr, u32 val)