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Revert "improve timings further"

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This reverts commit 764ee9ea1a.
This commit is contained in:
Jaklyy 2024-07-19 17:52:26 -04:00
parent 4f6db5a173
commit 36f4f2c5d3
2 changed files with 16 additions and 17 deletions
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11
src/ARM.h
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@ -278,13 +278,12 @@ public:
Cycles += std::max(numC, numI); Cycles += std::max(numC, numI);
} }
void AddCycles_CIF(s32 numI, s32 numL) void AddCycles_CIL(s32 numI, s32 numL)
{ {
// (code||internal)+forced // (code||internal)+forced interlock
// used by certain multiply instructions // used by S variants of multiply instructions on the ARM9
// seems likely that the execute stage occurs 2 cycles before the fetch stage ends....? // seems that instead of adding extra hardware logic to allow for handling the memory stage of the instructions during the execute stage
// could also be in some way related to interlock and the memory stage // it instead seems to force a two cycle interlock allowing for the interlocked cycle to be executed without any special logic + presumably an extra cycle to set flags
// though that doesn't explain why some non-S variants trigger this
s32 numC = CodeCycles; s32 numC = CodeCycles;
numI += 1; numI += 1;
Cycles += std::max(numC, numI) + numL; Cycles += std::max(numC, numI) + numL;

22
src/ARMInterpreter_ALU.cpp
View File

@ -777,7 +777,7 @@ void A_MUL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIF(1, 2); ((ARMv5*)cpu)->AddCycles_CIL(1, 2);
else else
cpu->AddCycles_CI(1); cpu->AddCycles_CI(1);
} }
@ -812,7 +812,7 @@ void A_MLA(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIF(1, 2); ((ARMv5*)cpu)->AddCycles_CIL(1, 2);
else else
cpu->AddCycles_CI(1); cpu->AddCycles_CI(1);
} }
@ -847,9 +847,9 @@ void A_UMULL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIF(1, 3); ((ARMv5*)cpu)->AddCycles_CIL(1, 2);
else else
((ARMv5*)cpu)->AddCycles_CIF(1, 1); cpu->AddCycles_CI(1);
} }
else else
{ {
@ -886,9 +886,9 @@ void A_UMLAL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIF(1, 3); ((ARMv5*)cpu)->AddCycles_CIL(1, 2);
else else
((ARMv5*)cpu)->AddCycles_CIF(1, 1); cpu->AddCycles_CI(1);
} }
else else
{ {
@ -922,9 +922,9 @@ void A_SMULL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIF(1, 3); ((ARMv5*)cpu)->AddCycles_CIL(1, 2);
else else
((ARMv5*)cpu)->AddCycles_CIF(1, 1); cpu->AddCycles_CI(1);
} }
else else
{ {
@ -961,9 +961,9 @@ void A_SMLAL(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
if (cpu->CurInstr & (1<<20)) if (cpu->CurInstr & (1<<20))
((ARMv5*)cpu)->AddCycles_CIF(1, 3); ((ARMv5*)cpu)->AddCycles_CIL(1, 2);
else else
((ARMv5*)cpu)->AddCycles_CIF(1, 1); cpu->AddCycles_CI(1);
} }
else else
{ {
@ -1497,7 +1497,7 @@ void T_MUL_REG(ARM* cpu)
if (cpu->Num == 0) if (cpu->Num == 0)
{ {
((ARMv5*)cpu)->AddCycles_CIF(1, 2); ((ARMv5*)cpu)->AddCycles_CIL(1, 2); // checkme?
} }
else else
{ {