mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-26 07:39:56 -06:00
GDB stub (#1583)
* gdbstub beginnings * gdbstub: finish gdb impl things, next up is integration with melonDS * holy fuck the gdbstub works * gdb breakpoints work, but there's a mysterious crash on continue * fix memory corruption that sometimes happened, and make resetting the console thru gdb work * remove some gdb debug printing * fix things in gdbstub * separate option for enabling gdbstub * add mode-dependent CPU registers * C++ize the GDBstub code * add gdbstub config in emu settings dialog * make sure gdb is disabled when jit is enabled * Remove unnecessary compiler flags, mark ARMJIT assembly code as no-execute-stack This hardens the binary a little bit against common exploitation methods * add option to wait for debugger attach on startup * only insert GNU stack notes on linux * disable gdbstub enable checkbox when jit is enabled * fix non-linux incompatibilities * enable gdbstub by default * fix issues with gdbstub settings disable stuff * format stuff * update gdb test code * Fix segfault when calling StubCallbacks->GetCPU() C++ overrides are hard. Please I'm just a lowly C programmer. * fix packet size not being sent correctly Thanks to @GlowingUmbreon on Github for troubleshooting this * fix select(2) calls (i should read docs more properly) * fix GDB command sequencing/parsing issue (hopefully) * [GDB] implement no-ack mode * fix sending ack on handshake * get lldb to work
This commit is contained in:
PoroCYon
121
src/ARM.h
121
src/ARM.h
@ -24,6 +24,10 @@
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#include "types.h"
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#include "NDS.h"
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#ifdef GDBSTUB_ENABLED
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#include "debug/GdbStub.h"
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#endif
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inline u32 ROR(u32 x, u32 n)
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{
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return (x >> (n&0x1F)) | (x << ((32-n)&0x1F));
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@ -39,6 +43,9 @@ const u32 ITCMPhysicalSize = 0x8000;
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const u32 DTCMPhysicalSize = 0x4000;
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class ARM
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#ifdef GDBSTUB_ENABLED
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: public Gdb::StubCallbacks
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#endif
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{
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public:
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ARM(u32 num);
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@ -93,6 +100,18 @@ public:
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if (v) CPSR |= 0x10000000;
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}
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inline bool ModeIs(u32 mode)
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{
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u32 cm = CPSR & 0x1f;
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mode &= 0x1f;
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if (mode == cm) return true;
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if (mode == 0x17) return cm >= 0x14 && cm <= 0x17; // abt
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if (mode == 0x1b) return cm >= 0x18 && cm <= 0x1b; // und
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return false;
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}
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void UpdateMode(u32 oldmode, u32 newmode, bool phony = false);
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void TriggerIRQ();
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@ -114,6 +133,7 @@ public:
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virtual void AddCycles_CDI() = 0;
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virtual void AddCycles_CD() = 0;
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void CheckGdbIncoming();
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u32 Num;
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@ -155,6 +175,9 @@ public:
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#endif
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static u32 ConditionTable[16];
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#ifdef GDBSTUB_ENABLED
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Gdb::GdbStub GdbStub;
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#endif
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protected:
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u8 (*BusRead8)(u32 addr);
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@ -163,6 +186,29 @@ protected:
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void (*BusWrite8)(u32 addr, u8 val);
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void (*BusWrite16)(u32 addr, u16 val);
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void (*BusWrite32)(u32 addr, u32 val);
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#ifdef GDBSTUB_ENABLED
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bool IsSingleStep;
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bool BreakReq;
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bool BreakOnStartup;
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public:
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int GetCPU() const override { return Num ? 7 : 9; }
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u32 ReadReg(Gdb::Register reg) override;
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void WriteReg(Gdb::Register reg, u32 v) override;
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u32 ReadMem(u32 addr, int size) override;
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void WriteMem(u32 addr, int size, u32 v) override;
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void ResetGdb() override;
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int RemoteCmd(const u8* cmd, size_t len) override;
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protected:
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#endif
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void GdbCheckA();
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void GdbCheckB();
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void GdbCheckC();
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};
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class ARMv5 : public ARM
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@ -171,51 +217,51 @@ public:
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ARMv5();
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~ARMv5();
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void Reset();
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void Reset() override;
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void DoSavestate(Savestate* file);
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void DoSavestate(Savestate* file) override;
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void UpdateRegionTimings(u32 addrstart, u32 addrend);
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void FillPipeline();
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void FillPipeline() override;
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void JumpTo(u32 addr, bool restorecpsr = false);
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void JumpTo(u32 addr, bool restorecpsr = false) override;
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void PrefetchAbort();
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void DataAbort();
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void Execute();
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void Execute() override;
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#ifdef JIT_ENABLED
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void ExecuteJIT();
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void ExecuteJIT() override;
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#endif
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// all code accesses are forced nonseq 32bit
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u32 CodeRead32(u32 addr, bool branch);
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void DataRead8(u32 addr, u32* val);
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void DataRead16(u32 addr, u32* val);
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void DataRead32(u32 addr, u32* val);
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void DataRead32S(u32 addr, u32* val);
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void DataWrite8(u32 addr, u8 val);
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void DataWrite16(u32 addr, u16 val);
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void DataWrite32(u32 addr, u32 val);
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void DataWrite32S(u32 addr, u32 val);
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void DataRead8(u32 addr, u32* val) override;
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void DataRead16(u32 addr, u32* val) override;
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void DataRead32(u32 addr, u32* val) override;
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void DataRead32S(u32 addr, u32* val) override;
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void DataWrite8(u32 addr, u8 val) override;
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void DataWrite16(u32 addr, u16 val) override;
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void DataWrite32(u32 addr, u32 val) override;
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void DataWrite32S(u32 addr, u32 val) override;
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void AddCycles_C()
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void AddCycles_C() override
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{
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// code only. always nonseq 32-bit for ARM9.
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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Cycles += numC;
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}
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void AddCycles_CI(s32 numI)
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void AddCycles_CI(s32 numI) override
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{
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// code+internal
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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Cycles += numC + numI;
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}
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void AddCycles_CDI()
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void AddCycles_CDI() override
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{
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// LDR/LDM cycles. ARM9 seems to skip the internal cycle there.
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// TODO: ITCM data fetches shouldn't be parallelized, they say
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@ -228,7 +274,7 @@ public:
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// Cycles += numC + numD;
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}
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void AddCycles_CD()
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void AddCycles_CD() override
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{
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// TODO: ITCM data fetches shouldn't be parallelized, they say
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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@ -302,6 +348,11 @@ public:
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u8* CurICacheLine;
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bool (*GetMemRegion)(u32 addr, bool write, NDS::MemRegion* region);
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#ifdef GDBSTUB_ENABLED
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u32 ReadMem(u32 addr, int size) override;
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void WriteMem(u32 addr, int size, u32 v) override;
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#endif
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};
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class ARMv4 : public ARM
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@ -309,15 +360,15 @@ class ARMv4 : public ARM
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public:
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ARMv4();
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void Reset();
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void Reset() override;
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void FillPipeline();
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void FillPipeline() override;
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void JumpTo(u32 addr, bool restorecpsr = false);
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void JumpTo(u32 addr, bool restorecpsr = false) override;
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void Execute();
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void Execute() override;
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#ifdef JIT_ENABLED
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void ExecuteJIT();
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void ExecuteJIT() override;
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#endif
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u16 CodeRead16(u32 addr)
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@ -330,14 +381,14 @@ public:
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return BusRead32(addr);
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}
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void DataRead8(u32 addr, u32* val)
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void DataRead8(u32 addr, u32* val) override
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{
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*val = BusRead8(addr);
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DataRegion = addr;
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DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
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}
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void DataRead16(u32 addr, u32* val)
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void DataRead16(u32 addr, u32* val) override
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{
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addr &= ~1;
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@ -346,7 +397,7 @@ public:
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DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
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}
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void DataRead32(u32 addr, u32* val)
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void DataRead32(u32 addr, u32* val) override
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{
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addr &= ~3;
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@ -355,7 +406,7 @@ public:
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DataCycles = NDS::ARM7MemTimings[addr >> 15][2];
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}
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void DataRead32S(u32 addr, u32* val)
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void DataRead32S(u32 addr, u32* val) override
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{
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addr &= ~3;
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@ -363,14 +414,14 @@ public:
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DataCycles += NDS::ARM7MemTimings[addr >> 15][3];
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}
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void DataWrite8(u32 addr, u8 val)
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void DataWrite8(u32 addr, u8 val) override
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{
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BusWrite8(addr, val);
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DataRegion = addr;
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DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
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}
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void DataWrite16(u32 addr, u16 val)
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void DataWrite16(u32 addr, u16 val) override
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{
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addr &= ~1;
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@ -379,7 +430,7 @@ public:
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DataCycles = NDS::ARM7MemTimings[addr >> 15][0];
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}
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void DataWrite32(u32 addr, u32 val)
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void DataWrite32(u32 addr, u32 val) override
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{
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addr &= ~3;
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@ -388,7 +439,7 @@ public:
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DataCycles = NDS::ARM7MemTimings[addr >> 15][2];
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}
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void DataWrite32S(u32 addr, u32 val)
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void DataWrite32S(u32 addr, u32 val) override
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{
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addr &= ~3;
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@ -397,19 +448,19 @@ public:
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}
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void AddCycles_C()
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void AddCycles_C() override
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{
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// code only. this code fetch is sequential.
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Cycles += NDS::ARM7MemTimings[CodeCycles][(CPSR&0x20)?1:3];
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}
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void AddCycles_CI(s32 num)
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void AddCycles_CI(s32 num) override
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{
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// code+internal. results in a nonseq code fetch.
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Cycles += NDS::ARM7MemTimings[CodeCycles][(CPSR&0x20)?0:2] + num;
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}
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void AddCycles_CDI()
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void AddCycles_CDI() override
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{
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// LDR/LDM cycles.
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s32 numC = NDS::ARM7MemTimings[CodeCycles][(CPSR&0x20)?0:2];
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@ -436,7 +487,7 @@ public:
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}
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}
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void AddCycles_CD()
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void AddCycles_CD() override
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{
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// TODO: max gain should be 5c when writing to mainRAM
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s32 numC = NDS::ARM7MemTimings[CodeCycles][(CPSR&0x20)?0:2];
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