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new block cache and much more...

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- more reliable code invalidation detection
- blocks aren't stopped at any branch, but are being followed
if possible to get larger blocks
- idle loop recognition
- optimised literal loads, load/store cycle counting
 and loads/stores from constant addresses
This commit is contained in:
RSDuck
2019-10-03 01:10:59 +02:00
parent 0e26aa4ede
commit 40b88ab05a
18 changed files with 1536 additions and 695 deletions
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12
src/CP15.cpp
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@ -562,9 +562,11 @@ void ARMv5::CP15Write(u32 id, u32 val)
case 0x750:
ARMJIT::InvalidateAll();
ICacheInvalidateAll();
return;
case 0x751:
ARMJIT::InvalidateByAddr(ARMJIT::TranslateAddr<0>(val));
ICacheInvalidateByAddr(val);
return;
case 0x752:
@ -814,7 +816,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
DataCycles = 1;
*(u8*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
ARMJIT::InvalidateITCM(addr & 0x7FFF);
#endif
return;
}
@ -838,7 +840,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
DataCycles = 1;
*(u16*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
ARMJIT::InvalidateITCM(addr & 0x7FFF);
#endif
return;
}
@ -862,8 +864,7 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
DataCycles = 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
ARMJIT::cache.ARM9_ITCM[((addr + 2) & 0x7FFF) >> 1] = NULL;
ARMJIT::InvalidateITCM(addr & 0x7FFF);
#endif
return;
}
@ -887,8 +888,7 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
DataCycles += 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
#ifdef JIT_ENABLED
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
ARMJIT::cache.ARM9_ITCM[((addr & 0x7FFF) >> 1) + 1] = NULL;
ARMJIT::InvalidateITCM(addr & 0x7FFF);
#endif
return;
}