mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-27 00:00:07 -06:00
Refactor the JIT to be object-oriented (#1879)
* Move TinyVector to a new file - So it's less sensitive to #include ordering * Forgot to include assert.h * Refactor ARMJIT_Memory into an object * Oops, forgot a declaration * Refactor ARMJIT to be contained in an object * Remove an unused function declaration * Add a missing #include * Remove a now-unused global * Use ARMJIT_Memory's own memory access functions * Fix some omissions in the ARM JIT * Move libandroid to be a member of ARMJIT_Memory instead of a global * Default-initialize most fields in ARMJIT_Compiler.h * Define NOOP_IF_NO_JIT * Finish refactoring the JIT to be object-oriented
This commit is contained in:
Jesse Talavera-Greenberg
committed by
GitHub
GitHub
parent
f2d7a29015
commit
544fefa27f
244
src/ARMJIT.cpp
244
src/ARMJIT.cpp
@ -17,7 +17,7 @@
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*/
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#include "ARMJIT.h"
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#include "ARMJIT_Memory.h"
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#include <string.h>
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#include <assert.h>
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#include <unordered_map>
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@ -58,49 +58,6 @@ namespace ARMJIT
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#define JIT_DEBUGPRINT(msg, ...)
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//#define JIT_DEBUGPRINT(msg, ...) Platform::Log(Platform::LogLevel::Debug, msg, ## __VA_ARGS__)
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Compiler* JITCompiler;
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int MaxBlockSize;
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bool LiteralOptimizations;
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bool BranchOptimizations;
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bool FastMemory;
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std::unordered_map<u32, JitBlock*> JitBlocks9;
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std::unordered_map<u32, JitBlock*> JitBlocks7;
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std::unordered_map<u32, JitBlock*> RestoreCandidates;
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TinyVector<u32> InvalidLiterals;
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AddressRange CodeIndexITCM[ITCMPhysicalSize / 512];
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AddressRange CodeIndexMainRAM[NDS::MainRAMMaxSize / 512];
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AddressRange CodeIndexSWRAM[NDS::SharedWRAMSize / 512];
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AddressRange CodeIndexVRAM[0x100000 / 512];
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AddressRange CodeIndexARM9BIOS[sizeof(NDS::ARM9BIOS) / 512];
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AddressRange CodeIndexARM7BIOS[sizeof(NDS::ARM7BIOS) / 512];
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AddressRange CodeIndexARM7WRAM[NDS::ARM7WRAMSize / 512];
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AddressRange CodeIndexARM7WVRAM[0x40000 / 512];
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AddressRange CodeIndexBIOS9DSi[0x10000 / 512];
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AddressRange CodeIndexBIOS7DSi[0x10000 / 512];
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AddressRange CodeIndexNWRAM_A[DSi::NWRAMSize / 512];
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AddressRange CodeIndexNWRAM_B[DSi::NWRAMSize / 512];
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AddressRange CodeIndexNWRAM_C[DSi::NWRAMSize / 512];
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u64 FastBlockLookupITCM[ITCMPhysicalSize / 2];
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u64 FastBlockLookupMainRAM[NDS::MainRAMMaxSize / 2];
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u64 FastBlockLookupSWRAM[NDS::SharedWRAMSize / 2];
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u64 FastBlockLookupVRAM[0x100000 / 2];
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u64 FastBlockLookupARM9BIOS[sizeof(NDS::ARM9BIOS) / 2];
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u64 FastBlockLookupARM7BIOS[sizeof(NDS::ARM7BIOS) / 2];
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u64 FastBlockLookupARM7WRAM[NDS::ARM7WRAMSize / 2];
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u64 FastBlockLookupARM7WVRAM[0x40000 / 2];
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u64 FastBlockLookupBIOS9DSi[0x10000 / 2];
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u64 FastBlockLookupBIOS7DSi[0x10000 / 2];
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u64 FastBlockLookupNWRAM_A[DSi::NWRAMSize / 2];
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u64 FastBlockLookupNWRAM_B[DSi::NWRAMSize / 2];
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u64 FastBlockLookupNWRAM_C[DSi::NWRAMSize / 2];
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const u32 CodeRegionSizes[ARMJIT_Memory::memregions_Count] =
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{
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0,
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@ -123,58 +80,14 @@ const u32 CodeRegionSizes[ARMJIT_Memory::memregions_Count] =
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DSi::NWRAMSize,
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};
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AddressRange* const CodeMemRegions[ARMJIT_Memory::memregions_Count] =
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{
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NULL,
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CodeIndexITCM,
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NULL,
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CodeIndexARM9BIOS,
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CodeIndexMainRAM,
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CodeIndexSWRAM,
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NULL,
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CodeIndexVRAM,
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CodeIndexARM7BIOS,
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CodeIndexARM7WRAM,
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NULL,
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NULL,
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CodeIndexARM7WVRAM,
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CodeIndexBIOS9DSi,
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CodeIndexBIOS7DSi,
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CodeIndexNWRAM_A,
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CodeIndexNWRAM_B,
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CodeIndexNWRAM_C
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};
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u64* const FastBlockLookupRegions[ARMJIT_Memory::memregions_Count] =
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{
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NULL,
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FastBlockLookupITCM,
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NULL,
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FastBlockLookupARM9BIOS,
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FastBlockLookupMainRAM,
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FastBlockLookupSWRAM,
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NULL,
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FastBlockLookupVRAM,
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FastBlockLookupARM7BIOS,
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FastBlockLookupARM7WRAM,
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NULL,
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NULL,
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FastBlockLookupARM7WVRAM,
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FastBlockLookupBIOS9DSi,
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FastBlockLookupBIOS7DSi,
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FastBlockLookupNWRAM_A,
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FastBlockLookupNWRAM_B,
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FastBlockLookupNWRAM_C
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};
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u32 LocaliseCodeAddress(u32 num, u32 addr)
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u32 ARMJIT::LocaliseCodeAddress(u32 num, u32 addr) const noexcept
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{
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int region = num == 0
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? ARMJIT_Memory::ClassifyAddress9(addr)
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: ARMJIT_Memory::ClassifyAddress7(addr);
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? Memory.ClassifyAddress9(addr)
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: Memory.ClassifyAddress7(addr);
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if (CodeMemRegions[region])
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return ARMJIT_Memory::LocaliseAddress(region, num, addr);
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return Memory.LocaliseAddress(region, num, addr);
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return 0;
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}
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@ -202,6 +115,26 @@ T SlowRead9(u32 addr, ARMv5* cpu)
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return val;
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}
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template <typename T, int ConsoleType>
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T SlowRead7(u32 addr)
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{
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u32 offset = addr & 0x3;
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addr &= ~(sizeof(T) - 1);
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T val;
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if (std::is_same<T, u32>::value)
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val = (ConsoleType == 0 ? NDS::ARM7Read32 : DSi::ARM7Read32)(addr);
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else if (std::is_same<T, u16>::value)
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val = (ConsoleType == 0 ? NDS::ARM7Read16 : DSi::ARM7Read16)(addr);
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else
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val = (ConsoleType == 0 ? NDS::ARM7Read8 : DSi::ARM7Read8)(addr);
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if (std::is_same<T, u32>::value)
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return ROR(val, offset << 3);
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else
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return val;
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}
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template <typename T, int ConsoleType>
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void SlowWrite9(u32 addr, ARMv5* cpu, u32 val)
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{
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@ -209,7 +142,7 @@ void SlowWrite9(u32 addr, ARMv5* cpu, u32 val)
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if (addr < cpu->ITCMSize)
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{
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CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
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cpu->JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
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*(T*)&cpu->ITCM[addr & 0x7FFF] = val;
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}
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else if ((addr & cpu->DTCMMask) == cpu->DTCMBase)
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@ -230,26 +163,6 @@ void SlowWrite9(u32 addr, ARMv5* cpu, u32 val)
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}
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}
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template <typename T, int ConsoleType>
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T SlowRead7(u32 addr)
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{
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u32 offset = addr & 0x3;
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addr &= ~(sizeof(T) - 1);
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T val;
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if (std::is_same<T, u32>::value)
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val = (ConsoleType == 0 ? NDS::ARM7Read32 : DSi::ARM7Read32)(addr);
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else if (std::is_same<T, u16>::value)
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val = (ConsoleType == 0 ? NDS::ARM7Read16 : DSi::ARM7Read16)(addr);
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else
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val = (ConsoleType == 0 ? NDS::ARM7Read8 : DSi::ARM7Read8)(addr);
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if (std::is_same<T, u32>::value)
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return ROR(val, offset << 3);
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else
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return val;
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}
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template <typename T, int ConsoleType>
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void SlowWrite7(u32 addr, u32 val)
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{
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@ -316,24 +229,13 @@ void SlowBlockTransfer7(u32 addr, u64* data, u32 num)
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INSTANTIATE_SLOWMEM(0)
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INSTANTIATE_SLOWMEM(1)
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void Init()
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{
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JITCompiler = new Compiler();
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ARMJIT_Memory::Init();
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}
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void DeInit()
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ARMJIT::~ARMJIT() noexcept
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{
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JitEnableWrite();
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ResetBlockCache();
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ARMJIT_Memory::DeInit();
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delete JITCompiler;
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JITCompiler = nullptr;
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}
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void Reset()
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void ARMJIT::Reset() noexcept
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{
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MaxBlockSize = Platform::GetConfigInt(Platform::JIT_MaxBlockSize);
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LiteralOptimizations = Platform::GetConfigBool(Platform::JIT_LiteralOptimizations);
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@ -348,7 +250,7 @@ void Reset()
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JitEnableWrite();
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ResetBlockCache();
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ARMJIT_Memory::Reset();
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Memory.Reset();
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}
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void FloodFillSetFlags(FetchedInstr instrs[], int start, u8 flags)
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@ -575,7 +477,7 @@ InterpreterFunc InterpretTHUMB[ARMInstrInfo::tk_Count] =
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};
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#undef F
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void RetireJitBlock(JitBlock* block)
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void ARMJIT::RetireJitBlock(JitBlock* block) noexcept
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{
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auto it = RestoreCandidates.find(block->InstrHash);
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if (it != RestoreCandidates.end())
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@ -589,7 +491,7 @@ void RetireJitBlock(JitBlock* block)
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}
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}
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void CompileBlock(ARM* cpu)
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void ARMJIT::CompileBlock(ARM* cpu) noexcept
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{
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bool thumb = cpu->CPSR & 0x20;
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@ -616,7 +518,7 @@ void CompileBlock(ARM* cpu)
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u64* entry = &FastBlockLookupRegions[localAddr >> 27][(localAddr & 0x7FFFFFF) / 2];
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*entry = ((u64)blockAddr | cpu->Num) << 32;
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*entry |= JITCompiler->SubEntryOffset(existingBlockIt->second->EntryPoint);
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*entry |= JITCompiler.SubEntryOffset(existingBlockIt->second->EntryPoint);
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return;
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}
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@ -717,7 +619,7 @@ void CompileBlock(ARM* cpu)
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nextInstr[1] = cpuv4->CodeRead32(r15);
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instrs[i].CodeCycles = cpu->CodeCycles;
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}
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instrs[i].Info = ARMInstrInfo::Decode(thumb, cpu->Num, instrs[i].Instr);
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instrs[i].Info = ARMInstrInfo::Decode(thumb, cpu->Num, instrs[i].Instr, LiteralOptimizations);
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hasMemoryInstr |= thumb
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? (instrs[i].Info.Kind >= ARMInstrInfo::tk_LDR_PCREL && instrs[i].Info.Kind <= ARMInstrInfo::tk_STMIA)
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@ -875,7 +777,7 @@ void CompileBlock(ARM* cpu)
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i++;
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bool canCompile = JITCompiler->CanCompile(thumb, instrs[i - 1].Info.Kind);
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bool canCompile = JITCompiler.CanCompile(thumb, instrs[i - 1].Info.Kind);
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bool secondaryFlagReadCond = !canCompile || (instrs[i - 1].BranchFlags & (branch_FollowCondTaken | branch_FollowCondNotTaken));
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if (instrs[i - 1].Info.ReadFlags != 0 || secondaryFlagReadCond)
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FloodFillSetFlags(instrs, i - 2, !secondaryFlagReadCond ? instrs[i - 1].Info.ReadFlags : 0xF);
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@ -956,7 +858,7 @@ void CompileBlock(ARM* cpu)
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FloodFillSetFlags(instrs, i - 1, 0xF);
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JitEnableWrite();
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block->EntryPoint = JITCompiler->CompileBlock(cpu, thumb, instrs, i, hasMemoryInstr);
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block->EntryPoint = JITCompiler.CompileBlock(cpu, thumb, instrs, i, hasMemoryInstr);
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JitEnableExecute();
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JIT_DEBUGPRINT("block start %p\n", block->EntryPoint);
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@ -977,7 +879,7 @@ void CompileBlock(ARM* cpu)
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AddressRange* region = CodeMemRegions[addressRanges[j] >> 27];
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if (!PageContainsCode(®ion[(addressRanges[j] & 0x7FFF000) / 512]))
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ARMJIT_Memory::SetCodeProtection(addressRanges[j] >> 27, addressRanges[j] & 0x7FFFFFF, true);
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Memory.SetCodeProtection(addressRanges[j] >> 27, addressRanges[j] & 0x7FFFFFF, true);
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AddressRange* range = ®ion[(addressRanges[j] & 0x7FFFFFF) / 512];
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range->Code |= addressMasks[j];
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@ -991,10 +893,10 @@ void CompileBlock(ARM* cpu)
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u64* entry = &FastBlockLookupRegions[(localAddr >> 27)][(localAddr & 0x7FFFFFF) / 2];
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*entry = ((u64)blockAddr | cpu->Num) << 32;
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*entry |= JITCompiler->SubEntryOffset(block->EntryPoint);
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*entry |= JITCompiler.SubEntryOffset(block->EntryPoint);
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}
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void InvalidateByAddr(u32 localAddr)
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void ARMJIT::InvalidateByAddr(u32 localAddr) noexcept
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{
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JIT_DEBUGPRINT("invalidating by addr %x\n", localAddr);
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@ -1031,7 +933,7 @@ void InvalidateByAddr(u32 localAddr)
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if (range->Blocks.Length == 0
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&& !PageContainsCode(®ion[(localAddr & 0x7FFF000) / 512]))
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{
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ARMJIT_Memory::SetCodeProtection(localAddr >> 27, localAddr & 0x7FFFFFF, false);
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Memory.SetCodeProtection(localAddr >> 27, localAddr & 0x7FFFFFF, false);
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}
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bool literalInvalidation = false;
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@ -1064,7 +966,7 @@ void InvalidateByAddr(u32 localAddr)
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if (otherRange->Blocks.Length == 0)
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{
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if (!PageContainsCode(&otherRegion[(addr & 0x7FFF000) / 512]))
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ARMJIT_Memory::SetCodeProtection(addr >> 27, addr & 0x7FFFFFF, false);
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Memory.SetCodeProtection(addr >> 27, addr & 0x7FFFFFF, false);
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otherRange->Code = 0;
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}
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@ -1088,7 +990,7 @@ void InvalidateByAddr(u32 localAddr)
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}
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}
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void CheckAndInvalidateITCM()
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void ARMJIT::CheckAndInvalidateITCM() noexcept
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{
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for (u32 i = 0; i < ITCMPhysicalSize; i+=512)
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{
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@ -1106,7 +1008,7 @@ void CheckAndInvalidateITCM()
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}
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}
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void CheckAndInvalidateWVRAM(int bank)
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void ARMJIT::CheckAndInvalidateWVRAM(int bank) noexcept
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{
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u32 start = bank == 1 ? 0x20000 : 0;
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for (u32 i = start; i < start+0x20000; i+=512)
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@ -1122,38 +1024,30 @@ void CheckAndInvalidateWVRAM(int bank)
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}
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}
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template <u32 num, int region>
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void CheckAndInvalidate(u32 addr)
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{
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u32 localAddr = ARMJIT_Memory::LocaliseAddress(region, num, addr);
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if (CodeMemRegions[region][(localAddr & 0x7FFFFFF) / 512].Code & (1 << ((localAddr & 0x1FF) / 16)))
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InvalidateByAddr(localAddr);
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}
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JitBlockEntry LookUpBlock(u32 num, u64* entries, u32 offset, u32 addr)
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JitBlockEntry ARMJIT::LookUpBlock(u32 num, u64* entries, u32 offset, u32 addr) noexcept
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{
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u64* entry = &entries[offset / 2];
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if (*entry >> 32 == (addr | num))
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return JITCompiler->AddEntryOffset((u32)*entry);
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return JITCompiler.AddEntryOffset((u32)*entry);
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return NULL;
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}
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void blockSanityCheck(u32 num, u32 blockAddr, JitBlockEntry entry)
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void ARMJIT::blockSanityCheck(u32 num, u32 blockAddr, JitBlockEntry entry) noexcept
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{
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u32 localAddr = LocaliseCodeAddress(num, blockAddr);
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assert(JITCompiler->AddEntryOffset((u32)FastBlockLookupRegions[localAddr >> 27][(localAddr & 0x7FFFFFF) / 2]) == entry);
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assert(JITCompiler.AddEntryOffset((u32)FastBlockLookupRegions[localAddr >> 27][(localAddr & 0x7FFFFFF) / 2]) == entry);
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}
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bool SetupExecutableRegion(u32 num, u32 blockAddr, u64*& entry, u32& start, u32& size)
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bool ARMJIT::SetupExecutableRegion(u32 num, u32 blockAddr, u64*& entry, u32& start, u32& size) noexcept
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{
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// amazingly ignoring the DTCM is the proper behaviour for code fetches
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int region = num == 0
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? ARMJIT_Memory::ClassifyAddress9(blockAddr)
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: ARMJIT_Memory::ClassifyAddress7(blockAddr);
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? Memory.ClassifyAddress9(blockAddr)
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: Memory.ClassifyAddress7(blockAddr);
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u32 memoryOffset;
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if (FastBlockLookupRegions[region]
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&& ARMJIT_Memory::GetMirrorLocation(region, num, blockAddr, memoryOffset, start, size))
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&& Memory.GetMirrorLocation(region, num, blockAddr, memoryOffset, start, size))
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{
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//printf("setup exec region %d %d %08x %08x %x %x\n", num, region, blockAddr, start, size, memoryOffset);
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entry = FastBlockLookupRegions[region] + memoryOffset / 2;
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@ -1162,28 +1056,28 @@ bool SetupExecutableRegion(u32 num, u32 blockAddr, u64*& entry, u32& start, u32&
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return false;
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}
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template void CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(u32);
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template void CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(u32);
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template void CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(u32);
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template void CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(u32);
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template void CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(u32);
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template void CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(u32);
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template void CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(u32);
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template void CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(u32);
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template void CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(u32);
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template void CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(u32);
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template void CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(u32);
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template void CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(u32);
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template void CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(u32);
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template void CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(u32);
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template void ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(u32);
|
||||
template void ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(u32);
|
||||
|
||||
void ResetBlockCache()
|
||||
void ARMJIT::ResetBlockCache() noexcept
|
||||
{
|
||||
Log(LogLevel::Debug, "Resetting JIT block cache...\n");
|
||||
|
||||
// could be replace through a function which only resets
|
||||
// the permissions but we're too lazy
|
||||
ARMJIT_Memory::Reset();
|
||||
Memory.Reset();
|
||||
|
||||
InvalidLiterals.Clear();
|
||||
for (int i = 0; i < ARMJIT_Memory::memregions_Count; i++)
|
||||
@ -1221,10 +1115,10 @@ void ResetBlockCache()
|
||||
JitBlocks9.clear();
|
||||
JitBlocks7.clear();
|
||||
|
||||
JITCompiler->Reset();
|
||||
JITCompiler.Reset();
|
||||
}
|
||||
|
||||
void JitEnableWrite()
|
||||
void ARMJIT::JitEnableWrite() noexcept
|
||||
{
|
||||
#if defined(__APPLE__) && defined(__aarch64__)
|
||||
if (__builtin_available(macOS 11.0, *))
|
||||
@ -1232,7 +1126,7 @@ void JitEnableWrite()
|
||||
#endif
|
||||
}
|
||||
|
||||
void JitEnableExecute()
|
||||
void ARMJIT::JitEnableExecute() noexcept
|
||||
{
|
||||
#if defined(__APPLE__) && defined(__aarch64__)
|
||||
if (__builtin_available(macOS 11.0, *))
|
||||
|
||||
Reference in New Issue
Block a user