mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-06-28 01:49:42 -06:00
Refactor the JIT to be object-oriented (#1879)
* Move TinyVector to a new file - So it's less sensitive to #include ordering * Forgot to include assert.h * Refactor ARMJIT_Memory into an object * Oops, forgot a declaration * Refactor ARMJIT to be contained in an object * Remove an unused function declaration * Add a missing #include * Remove a now-unused global * Use ARMJIT_Memory's own memory access functions * Fix some omissions in the ARM JIT * Move libandroid to be a member of ARMJIT_Memory instead of a global * Default-initialize most fields in ARMJIT_Compiler.h * Define NOOP_IF_NO_JIT * Finish refactoring the JIT to be object-oriented
This commit is contained in:
Jesse Talavera-Greenberg
committed by
GitHub
GitHub
parent
f2d7a29015
commit
544fefa27f
140
src/DSi.cpp
140
src/DSi.cpp
@ -28,10 +28,8 @@
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#include "DSi_SPI_TSC.h"
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#include "Platform.h"
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#ifdef JIT_ENABLED
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#include "ARMJIT.h"
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#include "ARMJIT_Memory.h"
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#endif
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#include "DSi_NDMA.h"
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#include "DSi_I2C.h"
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@ -99,11 +97,10 @@ void Set_SCFG_MC(u32 val);
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bool Init()
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{
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#ifndef JIT_ENABLED
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NWRAM_A = new u8[NWRAMSize];
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NWRAM_B = new u8[NWRAMSize];
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NWRAM_C = new u8[NWRAMSize];
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#endif
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// Memory is owned by ARMJIT_Memory, don't free it
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NWRAM_A = NDS::JIT->Memory.GetNWRAM_A();
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NWRAM_B = NDS::JIT->Memory.GetNWRAM_B();
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NWRAM_C = NDS::JIT->Memory.GetNWRAM_C();
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NDMAs[0] = new DSi_NDMA(0, 0, *NDS::GPU);
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NDMAs[1] = new DSi_NDMA(0, 1, *NDS::GPU);
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@ -127,15 +124,10 @@ bool Init()
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void DeInit()
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{
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#ifndef JIT_ENABLED
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delete[] NWRAM_A;
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delete[] NWRAM_B;
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delete[] NWRAM_C;
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// Memory is owned externally
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NWRAM_A = nullptr;
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NWRAM_B = nullptr;
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NWRAM_C = nullptr;
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#endif
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for (int i = 0; i < 8; i++)
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{
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@ -684,10 +676,8 @@ void SoftReset()
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// also, BPTWL[0x70] could be abused to quickly boot specific titles
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#ifdef JIT_ENABLED
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ARMJIT_Memory::Reset();
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ARMJIT::CheckAndInvalidateITCM();
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#endif
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NDS::JIT->Reset();
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NDS::JIT->CheckAndInvalidateITCM();
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NDS::ARM9->Reset();
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NDS::ARM7->Reset();
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@ -1043,9 +1033,7 @@ void MapNWRAM_A(u32 num, u8 val)
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u8 oldval = (MBK[0][mbkn] >> mbks) & 0xFF;
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if (oldval == val) return;
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#ifdef JIT_ENABLED
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ARMJIT_Memory::RemapNWRAM(0);
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#endif
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NDS::JIT->Memory.RemapNWRAM(0);
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MBK[0][mbkn] &= ~(0xFF << mbks);
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MBK[0][mbkn] |= (val << mbks);
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@ -1090,9 +1078,7 @@ void MapNWRAM_B(u32 num, u8 val)
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u8 oldval = (MBK[0][mbkn] >> mbks) & 0xFF;
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if (oldval == val) return;
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#ifdef JIT_ENABLED
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ARMJIT_Memory::RemapNWRAM(1);
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#endif
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NDS::JIT->Memory.RemapNWRAM(1);
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MBK[0][mbkn] &= ~(0xFF << mbks);
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MBK[0][mbkn] |= (val << mbks);
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@ -1139,9 +1125,7 @@ void MapNWRAM_C(u32 num, u8 val)
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u8 oldval = (MBK[0][mbkn] >> mbks) & 0xFF;
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if (oldval == val) return;
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#ifdef JIT_ENABLED
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ARMJIT_Memory::RemapNWRAM(2);
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#endif
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NDS::JIT->Memory.RemapNWRAM(2);
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MBK[0][mbkn] &= ~(0xFF << mbks);
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MBK[0][mbkn] |= (val << mbks);
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@ -1190,9 +1174,7 @@ void MapNWRAMRange(u32 cpu, u32 num, u32 val)
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u32 oldval = MBK[cpu][5+num];
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if (oldval == val) return;
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#ifdef JIT_ENABLED
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ARMJIT_Memory::RemapNWRAM(num);
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#endif
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NDS::JIT->Memory.RemapNWRAM(num);
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MBK[cpu][5+num] = val;
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@ -1468,9 +1450,7 @@ void ARM9Write8(u32 addr, u8 val)
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continue;
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u8* ptr = &NWRAM_A[page * 0x10000];
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*(u8*)&ptr[addr & 0xFFFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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}
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return;
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}
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@ -1488,9 +1468,7 @@ void ARM9Write8(u32 addr, u8 val)
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continue;
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u8* ptr = &NWRAM_B[page * 0x8000];
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*(u8*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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}
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return;
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}
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@ -1508,9 +1486,7 @@ void ARM9Write8(u32 addr, u8 val)
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continue;
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u8* ptr = &NWRAM_C[page * 0x8000];
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*(u8*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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}
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return;
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}
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@ -1523,9 +1499,7 @@ void ARM9Write8(u32 addr, u8 val)
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case 0x06000000:
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if (!(SCFG_EXT[0] & (1<<13))) return;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
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switch (addr & 0x00E00000)
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{
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case 0x00000000: NDS::GPU->WriteVRAM_ABG<u8>(addr, val); return;
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@ -1541,9 +1515,7 @@ void ARM9Write8(u32 addr, u8 val)
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return;
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case 0x0C000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u8*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
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return;
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}
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@ -1574,9 +1546,7 @@ void ARM9Write16(u32 addr, u16 val)
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continue;
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u8* ptr = &NWRAM_A[page * 0x10000];
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*(u16*)&ptr[addr & 0xFFFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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}
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return;
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}
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@ -1594,9 +1564,7 @@ void ARM9Write16(u32 addr, u16 val)
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continue;
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u8* ptr = &NWRAM_B[page * 0x8000];
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*(u16*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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}
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return;
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}
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@ -1614,9 +1582,7 @@ void ARM9Write16(u32 addr, u16 val)
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continue;
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u8* ptr = &NWRAM_C[page * 0x8000];
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*(u16*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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}
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return;
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}
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@ -1633,9 +1599,7 @@ void ARM9Write16(u32 addr, u16 val)
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return;
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case 0x0C000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u16*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
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return;
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}
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@ -1666,9 +1630,7 @@ void ARM9Write32(u32 addr, u32 val)
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continue;
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u8* ptr = &NWRAM_A[page * 0x10000];
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*(u32*)&ptr[addr & 0xFFFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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}
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return;
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}
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@ -1686,9 +1648,7 @@ void ARM9Write32(u32 addr, u32 val)
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continue;
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u8* ptr = &NWRAM_B[page * 0x8000];
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*(u32*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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}
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return;
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}
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@ -1706,9 +1666,7 @@ void ARM9Write32(u32 addr, u32 val)
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continue;
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u8* ptr = &NWRAM_C[page * 0x8000];
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*(u32*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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}
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return;
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}
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@ -1725,9 +1683,7 @@ void ARM9Write32(u32 addr, u32 val)
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return;
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case 0x0C000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u32*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
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return;
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}
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@ -1970,9 +1926,7 @@ void ARM7Write8(u32 addr, u8 val)
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continue;
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u8* ptr = &NWRAM_A[page * 0x10000];
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*(u8*)&ptr[addr & 0xFFFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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}
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return;
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}
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@ -1990,9 +1944,7 @@ void ARM7Write8(u32 addr, u8 val)
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continue;
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u8* ptr = &NWRAM_B[page * 0x8000];
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*(u8*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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}
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return;
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}
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@ -2010,9 +1962,7 @@ void ARM7Write8(u32 addr, u8 val)
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continue;
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u8* ptr = &NWRAM_C[page * 0x8000];
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*(u8*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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}
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return;
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}
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@ -2033,9 +1983,7 @@ void ARM7Write8(u32 addr, u8 val)
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case 0x0C000000:
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case 0x0C800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u8*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
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return;
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}
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@ -2067,9 +2015,7 @@ void ARM7Write16(u32 addr, u16 val)
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continue;
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u8* ptr = &NWRAM_A[page * 0x10000];
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*(u16*)&ptr[addr & 0xFFFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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}
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return;
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}
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@ -2087,9 +2033,7 @@ void ARM7Write16(u32 addr, u16 val)
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continue;
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u8* ptr = &NWRAM_B[page * 0x8000];
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*(u16*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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}
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return;
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}
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@ -2107,9 +2051,7 @@ void ARM7Write16(u32 addr, u16 val)
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continue;
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u8* ptr = &NWRAM_C[page * 0x8000];
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*(u16*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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}
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return;
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}
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@ -2130,9 +2072,7 @@ void ARM7Write16(u32 addr, u16 val)
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case 0x0C000000:
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case 0x0C800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u16*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
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return;
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}
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@ -2164,9 +2104,7 @@ void ARM7Write32(u32 addr, u32 val)
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continue;
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u8* ptr = &NWRAM_A[page * 0x10000];
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*(u32*)&ptr[addr & 0xFFFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_A>(addr);
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}
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return;
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}
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@ -2184,9 +2122,7 @@ void ARM7Write32(u32 addr, u32 val)
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continue;
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u8* ptr = &NWRAM_B[page * 0x8000];
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*(u32*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_B>(addr);
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}
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return;
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}
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@ -2204,9 +2140,7 @@ void ARM7Write32(u32 addr, u32 val)
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continue;
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u8* ptr = &NWRAM_C[page * 0x8000];
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*(u32*)&ptr[addr & 0x7FFF] = val;
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_NewSharedWRAM_C>(addr);
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}
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return;
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}
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@ -2227,9 +2161,7 @@ void ARM7Write32(u32 addr, u32 val)
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case 0x0C000000:
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case 0x0C800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u32*)&NDS::MainRAM[addr & NDS::MainRAMMask] = val;
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return;
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}
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