mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-27 00:00:07 -06:00
Refactor the JIT to be object-oriented (#1879)
* Move TinyVector to a new file - So it's less sensitive to #include ordering * Forgot to include assert.h * Refactor ARMJIT_Memory into an object * Oops, forgot a declaration * Refactor ARMJIT to be contained in an object * Remove an unused function declaration * Add a missing #include * Remove a now-unused global * Use ARMJIT_Memory's own memory access functions * Fix some omissions in the ARM JIT * Move libandroid to be a member of ARMJIT_Memory instead of a global * Default-initialize most fields in ARMJIT_Compiler.h * Define NOOP_IF_NO_JIT * Finish refactoring the JIT to be object-oriented
This commit is contained in:
Jesse Talavera-Greenberg
committed by
GitHub
GitHub
parent
f2d7a29015
commit
544fefa27f
136
src/NDS.cpp
136
src/NDS.cpp
@ -35,16 +35,13 @@
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#include "Platform.h"
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#include "FreeBIOS.h"
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#ifdef JIT_ENABLED
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#include "ARMJIT.h"
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#include "ARMJIT_Memory.h"
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#endif
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#include "DSi.h"
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#include "DSi_SPI_TSC.h"
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#include "DSi_NWifi.h"
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#include "DSi_Camera.h"
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#include "DSi_DSP.h"
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#include "ARMJIT.h"
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#include "ARMJIT_Memory.h"
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using namespace Platform;
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@ -186,6 +183,7 @@ class Wifi* Wifi;
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std::unique_ptr<NDSCart::NDSCartSlot> NDSCartSlot;
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std::unique_ptr<GBACart::GBACartSlot> GBACartSlot;
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std::unique_ptr<Melon::GPU> GPU;
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std::unique_ptr<ARMJIT::ARMJIT> JIT;
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class AREngine* AREngine;
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bool Running;
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@ -205,17 +203,15 @@ bool Init()
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RegisterEventFunc(Event_Div, 0, DivDone);
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RegisterEventFunc(Event_Sqrt, 0, SqrtDone);
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GPU = std::make_unique<Melon::GPU>();
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ARM9 = new ARMv5(*GPU);
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ARM7 = new ARMv4(*GPU);
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JIT = std::make_unique<ARMJIT::ARMJIT>();
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GPU = std::make_unique<Melon::GPU>(*JIT);
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#ifdef JIT_ENABLED
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ARMJIT::Init();
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#else
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MainRAM = new u8[0x1000000];
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ARM7WRAM = new u8[ARM7WRAMSize];
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SharedWRAM = new u8[SharedWRAMSize];
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#endif
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MainRAM = JIT->Memory.GetMainRAM();
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SharedWRAM = JIT->Memory.GetSharedWRAM();
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ARM7WRAM = JIT->Memory.GetARM7WRAM();
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ARM9 = new ARMv5(*JIT, *GPU);
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ARM7 = new ARMv4(*JIT, *GPU);
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DMAs[0] = new DMA(0, 0, *GPU);
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DMAs[1] = new DMA(0, 1, *GPU);
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@ -242,10 +238,6 @@ bool Init()
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void DeInit()
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{
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#ifdef JIT_ENABLED
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ARMJIT::DeInit();
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#endif
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delete ARM9; ARM9 = nullptr;
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delete ARM7; ARM7 = nullptr;
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@ -270,6 +262,8 @@ void DeInit()
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UnregisterEventFunc(Event_Div, 0);
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UnregisterEventFunc(Event_Sqrt, 0);
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JIT = nullptr;
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}
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@ -548,9 +542,7 @@ void Reset()
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// BIOS files are now loaded by the frontend
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#ifdef JIT_ENABLED
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ARMJIT::Reset();
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#endif
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JIT->Reset();
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if (ConsoleType == 1)
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{
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@ -869,8 +861,8 @@ bool DoSavestate(Savestate* file)
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#ifdef JIT_ENABLED
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if (!file->Saving)
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{
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ARMJIT::ResetBlockCache();
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ARMJIT_Memory::Reset();
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JIT->ResetBlockCache();
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JIT->Memory.Reset();
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}
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#endif
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@ -1401,9 +1393,7 @@ void MapSharedWRAM(u8 val)
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if (val == WRAMCnt)
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return;
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#ifdef JIT_ENABLED
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ARMJIT_Memory::RemapSWRAM();
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#endif
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NDS::JIT->Memory.RemapSWRAM();
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WRAMCnt = val;
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@ -2315,18 +2305,14 @@ void ARM9Write8(u32 addr, u8 val)
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switch (addr & 0xFF000000)
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{
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case 0x02000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u8*)&MainRAM[addr & MainRAMMask] = val;
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return;
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case 0x03000000:
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if (SWRAM_ARM9.Mem)
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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*(u8*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask] = val;
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}
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return;
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@ -2361,18 +2347,14 @@ void ARM9Write16(u32 addr, u16 val)
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switch (addr & 0xFF000000)
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{
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case 0x02000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u16*)&MainRAM[addr & MainRAMMask] = val;
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return;
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case 0x03000000:
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if (SWRAM_ARM9.Mem)
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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*(u16*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask] = val;
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}
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return;
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@ -2387,9 +2369,7 @@ void ARM9Write16(u32 addr, u16 val)
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return;
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case 0x06000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
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switch (addr & 0x00E00000)
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{
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case 0x00000000: GPU->WriteVRAM_ABG<u16>(addr, val); return;
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@ -2429,18 +2409,14 @@ void ARM9Write32(u32 addr, u32 val)
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switch (addr & 0xFF000000)
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{
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case 0x02000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u32*)&MainRAM[addr & MainRAMMask] = val;
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return ;
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case 0x03000000:
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if (SWRAM_ARM9.Mem)
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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*(u32*)&SWRAM_ARM9.Mem[addr & SWRAM_ARM9.Mask] = val;
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}
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return;
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@ -2455,9 +2431,7 @@ void ARM9Write32(u32 addr, u32 val)
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return;
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case 0x06000000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<0, ARMJIT_Memory::memregion_VRAM>(addr);
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switch (addr & 0x00E00000)
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{
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case 0x00000000: GPU->WriteVRAM_ABG<u32>(addr, val); return;
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@ -2738,34 +2712,26 @@ void ARM7Write8(u32 addr, u8 val)
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{
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case 0x02000000:
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case 0x02800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u8*)&MainRAM[addr & MainRAMMask] = val;
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return;
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case 0x03000000:
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if (SWRAM_ARM7.Mem)
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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*(u8*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask] = val;
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return;
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}
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else
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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*(u8*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
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return;
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}
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case 0x03800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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*(u8*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
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return;
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@ -2775,9 +2741,7 @@ void ARM7Write8(u32 addr, u8 val)
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case 0x06000000:
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case 0x06800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
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GPU->WriteVRAM_ARM7<u8>(addr, val);
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return;
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@ -2808,34 +2772,26 @@ void ARM7Write16(u32 addr, u16 val)
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{
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case 0x02000000:
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case 0x02800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u16*)&MainRAM[addr & MainRAMMask] = val;
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return;
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case 0x03000000:
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if (SWRAM_ARM7.Mem)
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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*(u16*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask] = val;
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return;
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}
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else
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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*(u16*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
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return;
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}
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case 0x03800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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*(u16*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
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return;
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@ -2854,9 +2810,7 @@ void ARM7Write16(u32 addr, u16 val)
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case 0x06000000:
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case 0x06800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
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GPU->WriteVRAM_ARM7<u16>(addr, val);
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return;
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@ -2889,34 +2843,26 @@ void ARM7Write32(u32 addr, u32 val)
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{
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case 0x02000000:
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case 0x02800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_MainRAM>(addr);
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*(u32*)&MainRAM[addr & MainRAMMask] = val;
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return;
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case 0x03000000:
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if (SWRAM_ARM7.Mem)
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_SharedWRAM>(addr);
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*(u32*)&SWRAM_ARM7.Mem[addr & SWRAM_ARM7.Mask] = val;
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return;
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}
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else
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{
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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*(u32*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
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return;
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}
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case 0x03800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_WRAM7>(addr);
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*(u32*)&ARM7WRAM[addr & (ARM7WRAMSize - 1)] = val;
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return;
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@ -2936,9 +2882,7 @@ void ARM7Write32(u32 addr, u32 val)
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case 0x06000000:
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case 0x06800000:
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#ifdef JIT_ENABLED
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ARMJIT::CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
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#endif
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NDS::JIT->CheckAndInvalidate<1, ARMJIT_Memory::memregion_VWRAM>(addr);
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GPU->WriteVRAM_ARM7<u32>(addr, val);
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return;
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