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* scheduler revamp, simpler design

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* fix dumb bug of the year: ARM LDR opcodes would accidentally read twice, which fucked with things like the IPC FIFO.
This commit is contained in:
StapleButter
2017-01-31 03:54:51 +01:00
parent 348bbd8cb8
commit 594286ee5d
10 changed files with 274 additions and 108 deletions
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4
ARMInterpreter_LoadStore.cpp
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@ -82,7 +82,7 @@ namespace ARMInterpreter
#define A_LDR \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 val = ROR(cpu->DataRead32(offset), ((offset&0x3)<<3)); \
u32 val = cpu->DataRead32(offset); val = ROR(val, ((offset&0x3)<<3)); \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
cpu->Cycles += 1; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
@ -97,7 +97,7 @@ namespace ARMInterpreter
#define A_LDR_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 val = ROR(cpu->DataRead32(addr, cpu->CurInstr & (1<<21)), ((addr&0x3)<<3)); \
u32 val = cpu->DataRead32(addr, cpu->CurInstr & (1<<21)); val = ROR(val, ((addr&0x3)<<3)); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
cpu->Cycles += 1; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \