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https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
some tiny A64 optimisations
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@ -323,6 +323,8 @@ void Compiler::Comp_Arithmetic(int op, bool S, ARM64Reg rd, ARM64Reg rn, Op2 op2
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case 0x5: // ADC
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case 0x5: // ADC
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UBFX(W2, RCPSR, 29, 1);
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UBFX(W2, RCPSR, 29, 1);
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if (S)
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if (S)
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{
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if (op2.IsImm)
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{
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{
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CVInGPR = true;
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CVInGPR = true;
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ADDS(W1, rn, W2);
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ADDS(W1, rn, W2);
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@ -336,6 +338,17 @@ void Compiler::Comp_Arithmetic(int op, bool S, ARM64Reg rd, ARM64Reg rn, Op2 op2
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CSINC(W3, W3, WZR, CC_VC);
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CSINC(W3, W3, WZR, CC_VC);
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}
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}
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else
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else
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{
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if (op2.Reg.ShiftAmount > 0)
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{
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MOV(W0, op2.Reg.Rm, op2.ToArithOption());
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op2 = Op2(W0, ST_LSL, 0);
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}
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CMP(W2, 1);
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ADCS(rd, rn, op2.Reg.Rm);
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}
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}
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else
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{
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{
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ADD(W1, rn, W2);
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ADD(W1, rn, W2);
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if (op2.IsImm)
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if (op2.IsImm)
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@ -346,6 +359,18 @@ void Compiler::Comp_Arithmetic(int op, bool S, ARM64Reg rd, ARM64Reg rn, Op2 op2
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break;
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break;
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case 0x6: // SBC
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case 0x6: // SBC
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UBFX(W2, RCPSR, 29, 1);
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UBFX(W2, RCPSR, 29, 1);
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if (S && !op2.IsImm)
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{
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if (op2.Reg.ShiftAmount > 0)
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{
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MOV(W0, op2.Reg.Rm, op2.ToArithOption());
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op2 = Op2(W0, ST_LSL, 0);
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}
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CMP(W2, 1);
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SBCS(rd, rn, op2.Reg.Rm);
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}
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else
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{
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// W1 = -op2 - 1
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// W1 = -op2 - 1
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if (op2.IsImm)
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if (op2.IsImm)
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MOVI2R(W1, ~op2.Imm);
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MOVI2R(W1, ~op2.Imm);
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@ -366,6 +391,7 @@ void Compiler::Comp_Arithmetic(int op, bool S, ARM64Reg rd, ARM64Reg rn, Op2 op2
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ADD(W1, W2, W1);
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ADD(W1, W2, W1);
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ADD(rd, rn, W1);
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ADD(rd, rn, W1);
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}
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}
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}
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break;
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break;
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case 0x7: // RSC
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case 0x7: // RSC
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UBFX(W2, RCPSR, 29, 1);
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UBFX(W2, RCPSR, 29, 1);
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@ -532,24 +558,10 @@ void Compiler::A_Comp_ALUMovOp()
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MOVI2R(rd, op2.Imm);
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MOVI2R(rd, op2.Imm);
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}
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}
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else
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else
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{
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// ORR with shifted operand has cycles latency
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if (op2.Reg.ShiftAmount > 0)
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{
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switch (op2.Reg.ShiftType)
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{
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case ST_LSL: LSL(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
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case ST_LSR: LSR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
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case ST_ASR: ASR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
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case ST_ROR: ROR(rd, op2.Reg.Rm, op2.Reg.ShiftAmount); break;
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}
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}
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else
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{
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{
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MOV(rd, op2.Reg.Rm, op2.ToArithOption());
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MOV(rd, op2.Reg.Rm, op2.ToArithOption());
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}
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}
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}
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}
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}
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if (S)
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if (S)
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{
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{
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@ -1607,7 +1607,21 @@ void ARM64XEmitter::BICS(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shif
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void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift)
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void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm, ArithOption Shift)
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{
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{
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if (Shift.GetType() == ArithOption::TYPE_SHIFTEDREG)
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{
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switch (Shift.GetShiftType())
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{
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case ST_LSL: LSL(Rd, Rm, Shift.GetShiftAmount()); break;
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case ST_LSR: LSR(Rd, Rm, Shift.GetShiftAmount()); break;
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case ST_ASR: ASR(Rd, Rm, Shift.GetShiftAmount()); break;
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case ST_ROR: ROR(Rd, Rm, Shift.GetShiftAmount()); break;
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default: ASSERT_MSG(DYNA_REC, false, "Invalid shift type"); break;
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}
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}
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else
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{
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ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift);
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ORR(Rd, Is64Bit(Rd) ? ZR : WZR, Rm, Shift);
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}
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}
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}
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void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm)
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void ARM64XEmitter::MOV(ARM64Reg Rd, ARM64Reg Rm)
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@ -469,6 +469,8 @@ public:
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}
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}
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TypeSpecifier GetType() const { return m_type; }
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TypeSpecifier GetType() const { return m_type; }
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ARM64Reg GetReg() const { return m_destReg; }
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ARM64Reg GetReg() const { return m_destReg; }
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ShiftType GetShiftType() const { return m_shifttype; }
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u32 GetShiftAmount() const { return m_shift; }
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u32 GetData() const
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u32 GetData() const
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{
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{
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switch (m_type)
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switch (m_type)
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