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https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
moar shit
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@ -196,6 +196,164 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write16(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_STRH_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write16(addr, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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// TODO: CHECK LDRD/STRD TIMINGS!!
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#define A_LDRD \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->R[r ] = cpu->Read32(offset ); \
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cpu->R[r+1] = cpu->Read32(offset+4); \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset);
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#define A_LDRD_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->R[r ] = cpu->Read32(addr ); \
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cpu->R[r+1] = cpu->Read32(addr+4); \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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#define A_STRD \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->Write32(offset , cpu->R[r ]); \
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cpu->Write32(offset+4, cpu->R[r+1]); \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_STRD_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->Write32(offset , cpu->R[r ]); \
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cpu->Write32(offset+4, cpu->R[r+1]); \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_LDRH \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(offset); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_LDRH_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(addr); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_LDRSB \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s8)cpu->Read8(offset); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_LDRSB_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s8)cpu->Read8(addr); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_LDRSH \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(offset); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_LDRSH_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(addr); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_IMPLEMENT_HD_LDRSTR(x) \
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\
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s32 A_##x##_IMM(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_IMM \
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A_##x \
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} \
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\
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s32 A_##x##_REG(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_REG \
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A_##x \
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} \
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s32 A_##x##_POST_IMM(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_IMM \
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A_##x##_POST \
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} \
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\
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s32 A_##x##_POST_REG(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_REG \
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A_##x##_POST \
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}
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A_IMPLEMENT_HD_LDRSTR(STRH)
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A_IMPLEMENT_HD_LDRSTR(LDRD)
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A_IMPLEMENT_HD_LDRSTR(STRD)
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A_IMPLEMENT_HD_LDRSTR(LDRH)
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A_IMPLEMENT_HD_LDRSTR(LDRSB)
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A_IMPLEMENT_HD_LDRSTR(LDRSH)
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// ---- THUMB -----------------------
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s32 T_LDR_PCREL(ARM* cpu)
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{
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u32 addr = cpu->R[15] + ((cpu->CurInstr & 0xFF) << 2);
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cpu->R[(cpu->CurInstr >> 8) & 0x7] = cpu->Read32(addr);
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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}
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s32 T_STR_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->Write32(addr, cpu->R[cpu->CurInstr & 0x7]);
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return C_N(2) + cpu->MemWaitstate(3, addr);
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}
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s32 T_STRB_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->Write8(addr, cpu->R[cpu->CurInstr & 0x7]);
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return C_N(2) + cpu->MemWaitstate(3, addr);
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}
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s32 T_LDR_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->R[cpu->CurInstr & 0x7] = cpu->Read32(addr);
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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}
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s32 T_LDRB_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->R[cpu->CurInstr & 0x7] = cpu->Read8(addr);
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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}
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}
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