diff --git a/src/NDSCart.cpp b/src/NDSCart.cpp
index a98f8c8e..4266639a 100644
--- a/src/NDSCart.cpp
+++ b/src/NDSCart.cpp
@@ -1260,8 +1260,14 @@ void WriteROMCnt(u32 val)
     // TODO: advance read position if bit28 is set
 
     u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
-    u32 cmddelay = 8 + (ROMCnt & 0x1FFF);
-    if (datasize) cmddelay += ((ROMCnt >> 16) & 0x3F);
+    u32 cmddelay = 8;
+
+    // delays are only applied when the WR bit is cleared
+    if (!(ROMCnt & (1<<30)))
+    {
+        cmddelay += (ROMCnt & 0x1FFF);
+        if (datasize) cmddelay += ((ROMCnt >> 16) & 0x3F);
+    }
 
     if (datasize == 0)
         NDS::ScheduleEvent(NDS::Event_ROMTransfer, false, xfercycle*cmddelay, ROMEndTransfer, 0);