mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
redesign main emu loop to use timestamps instead of being a trainwreck
* cleaner code * faster in some cases * more accurate (on-demand compensation for timers and GPU) * less prone to desyncs * overall betterer
This commit is contained in:
StapleButter
283
src/DMA.cpp
283
src/DMA.cpp
@ -45,6 +45,8 @@
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// * applied to all accesses for mainRAM->mainRAM, resulting in timings of 16-18 cycles per unit
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//
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// TODO: GBA slot
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// TODO: re-add initial NS delay
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// TODO: timings are nonseq when address is fixed/decrementing
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DMA::DMA(u32 cpu, u32 num)
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@ -186,160 +188,94 @@ void DMA::Start()
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NDS::StopCPU(CPU, 1<<Num);
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}
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s32 DMA::Run(s32 cycles)
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void DMA::Run()
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{
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if (!Running)
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return cycles;
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if (!Running) return;
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if (CPU == 0) return Run9();
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else return Run7();
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}
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#ifdef DEBUG_CHECK_DESYNC
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s32 startc = cycles;
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#endif // DEBUG_CHECK_DESYNC
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void DMA::Run9()
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{
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if (NDS::ARM9Timestamp >= NDS::ARM9Target) return;
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Executing = true;
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// add NS penalty for first accesses in burst
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// note: this seems to only apply when starting DMA 'in the void'
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// for example, the aging cart DMA PRIORITY test:
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// starts a big DMA immediately, and a small DMA upon HBlank
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// each pulling from a timer incrementing once per cycle
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// it expects that the values be increasing linearly (2c/unit)
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// even as the small DMA starts and ends
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bool burststart = (Running == 2);
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Running = 1;
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s32 unitcycles;
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s32 lastcycles = cycles;
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//s32 lastcycles = cycles;
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if (!(Cnt & 0x04000000))
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if (!(Cnt & (1<<26)))
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{
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if (CPU == 0)
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][0] + NDS::ARM9MemTimings[CurDstAddr >> 14][0];
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}
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else
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][1] + NDS::ARM9MemTimings[CurDstAddr >> 14][1];
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if ((CurSrcAddr >> 24) == (CurDstAddr >> 24))
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unitcycles++;
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if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][0] + NDS::ARM9MemTimings[CurDstAddr >> 14][0]);
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cycles += unitcycles;
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}
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}
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][0] + NDS::ARM9MemTimings[CurDstAddr >> 14][0];
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}
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else
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{
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][0] + NDS::ARM7MemTimings[CurDstAddr >> 15][0];
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}
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else
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][1] + NDS::ARM7MemTimings[CurDstAddr >> 15][1];
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if ((CurSrcAddr >> 23) == (CurDstAddr >> 23))
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unitcycles++;
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][1] + NDS::ARM9MemTimings[CurDstAddr >> 14][1];
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if ((CurSrcAddr >> 24) == (CurDstAddr >> 24))
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unitcycles++;
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if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][0] + NDS::ARM7MemTimings[CurDstAddr >> 15][0]);
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cycles += unitcycles;
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}
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}
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/*if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][0] + NDS::ARM9MemTimings[CurDstAddr >> 14][0]);
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cycles += unitcycles;
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}*/
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}
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u16 (*readfn)(u32) = CPU ? NDS::ARM7Read16 : NDS::ARM9Read16;
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void (*writefn)(u32,u16) = CPU ? NDS::ARM7Write16 : NDS::ARM9Write16;
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while (IterCount > 0 && !Stall)
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{
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cycles -= unitcycles;
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NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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NDS::RunTightTimers(CPU, lastcycles-cycles);
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lastcycles = cycles;
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writefn(CurDstAddr, readfn(CurSrcAddr));
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NDS::ARM9Write16(CurDstAddr, NDS::ARM9Read16(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<1;
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CurDstAddr += DstAddrInc<<1;
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IterCount--;
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RemCount--;
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if (cycles <= 0) break;
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if (NDS::ARM9Timestamp >= NDS::ARM9Target) break;
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}
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}
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else
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{
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if (CPU == 0)
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2];
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}
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else
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][3] + NDS::ARM9MemTimings[CurDstAddr >> 14][3];
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if ((CurSrcAddr >> 24) == (CurDstAddr >> 24))
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unitcycles++;
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else if ((CurSrcAddr >> 24) == 0x02)
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unitcycles--;
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if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]);
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cycles += unitcycles;
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}
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}
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2];
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}
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else
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{
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2];
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}
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else
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][3] + NDS::ARM7MemTimings[CurDstAddr >> 15][3];
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if ((CurSrcAddr >> 23) == (CurDstAddr >> 23))
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unitcycles++;
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else if ((CurSrcAddr >> 24) == 0x02)
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unitcycles--;
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][3] + NDS::ARM9MemTimings[CurDstAddr >> 14][3];
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if ((CurSrcAddr >> 24) == (CurDstAddr >> 24))
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unitcycles++;
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else if ((CurSrcAddr >> 24) == 0x02)
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unitcycles--;
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if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]);
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cycles += unitcycles;
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}
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}
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/*if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]);
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cycles += unitcycles;
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}*/
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}
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u32 (*readfn)(u32) = CPU ? NDS::ARM7Read32 : NDS::ARM9Read32;
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void (*writefn)(u32,u32) = CPU ? NDS::ARM7Write32 : NDS::ARM9Write32;
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while (IterCount > 0 && !Stall)
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{
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cycles -= unitcycles;
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NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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NDS::RunTightTimers(CPU, lastcycles-cycles);
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lastcycles = cycles;
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writefn(CurDstAddr, readfn(CurSrcAddr));
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NDS::ARM9Write32(CurDstAddr, NDS::ARM9Read32(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<2;
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CurDstAddr += DstAddrInc<<2;
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IterCount--;
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RemCount--;
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if (cycles <= 0) break;
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if (NDS::ARM9Timestamp >= NDS::ARM9Target) break;
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}
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}
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@ -351,34 +287,131 @@ s32 DMA::Run(s32 cycles)
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if (IterCount == 0)
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{
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Running = 0;
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NDS::ResumeCPU(CPU, 1<<Num);
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NDS::ResumeCPU(0, 1<<Num);
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if (StartMode == 0x07)
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GPU3D::CheckFIFODMA();
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}
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#ifdef DEBUG_CHECK_DESYNC
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if (CPU) NDS::dbg_CyclesARM7 += (startc-cycles);
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else NDS::dbg_CyclesARM9 += (startc-cycles);
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#endif // DEBUG_CHECK_DESYNC
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return cycles;
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return;
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}
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if (!(Cnt & 0x02000000))
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Cnt &= ~0x80000000;
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if (!(Cnt & (1<<25)))
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Cnt &= ~(1<<31);
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if (Cnt & 0x40000000)
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NDS::SetIRQ(CPU, NDS::IRQ_DMA0 + Num);
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if (Cnt & (1<<30))
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NDS::SetIRQ(0, NDS::IRQ_DMA0 + Num);
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Running = 0;
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InProgress = false;
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NDS::ResumeCPU(CPU, 1<<Num);
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#ifdef DEBUG_CHECK_DESYNC
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if (CPU) NDS::dbg_CyclesARM7 += (startc-cycles);
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else NDS::dbg_CyclesARM9 += (startc-cycles);
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#endif // DEBUG_CHECK_DESYNC
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return cycles;
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NDS::ResumeCPU(0, 1<<Num);
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}
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void DMA::Run7()
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{
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if (NDS::ARM7Timestamp >= NDS::ARM7Target) return;
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Executing = true;
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// add NS penalty for first accesses in burst
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bool burststart = (Running == 2);
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Running = 1;
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s32 unitcycles;
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//s32 lastcycles = cycles;
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if (!(Cnt & (1<<26)))
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{
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][0] + NDS::ARM7MemTimings[CurDstAddr >> 15][0];
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}
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else
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][1] + NDS::ARM7MemTimings[CurDstAddr >> 15][1];
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if ((CurSrcAddr >> 23) == (CurDstAddr >> 23))
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unitcycles++;
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/*if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][0] + NDS::ARM7MemTimings[CurDstAddr >> 15][0]);
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cycles += unitcycles;
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}*/
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}
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while (IterCount > 0 && !Stall)
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{
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NDS::ARM7Timestamp += unitcycles;
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NDS::ARM7Write16(CurDstAddr, NDS::ARM7Read16(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<1;
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CurDstAddr += DstAddrInc<<1;
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IterCount--;
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RemCount--;
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if (NDS::ARM7Timestamp >= NDS::ARM7Target) break;
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}
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}
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else
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{
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2];
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}
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else
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][3] + NDS::ARM7MemTimings[CurDstAddr >> 15][3];
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if ((CurSrcAddr >> 23) == (CurDstAddr >> 23))
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unitcycles++;
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else if ((CurSrcAddr >> 24) == 0x02)
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unitcycles--;
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/*if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]);
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cycles += unitcycles;
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}*/
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}
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while (IterCount > 0 && !Stall)
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{
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NDS::ARM7Timestamp += unitcycles;
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NDS::ARM7Write32(CurDstAddr, NDS::ARM7Read32(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<2;
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CurDstAddr += DstAddrInc<<2;
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IterCount--;
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RemCount--;
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if (NDS::ARM7Timestamp >= NDS::ARM7Target) break;
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}
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}
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Executing = false;
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Stall = false;
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if (RemCount)
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{
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if (IterCount == 0)
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{
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Running = 0;
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NDS::ResumeCPU(1, 1<<Num);
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}
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return;
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}
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if (!(Cnt & (1<<25)))
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Cnt &= ~(1<<31);
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if (Cnt & (1<<30))
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NDS::SetIRQ(1, NDS::IRQ_DMA0 + Num);
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Running = 0;
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InProgress = false;
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NDS::ResumeCPU(1, 1<<Num);
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}
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