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https://github.com/melonDS-emu/melonDS.git
synced 2024-11-15 05:47:43 -07:00
GPU2D: allow writes to DISPCNT, master brightness, capture, dispFIFO regardless of POWCNT.
fixes #665
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@ -35,9 +35,6 @@
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// * [Gericom] bit15 is used as bottom green bit for palettes. TODO: check where this applies.
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// * [Gericom] bit15 is used as bottom green bit for palettes. TODO: check where this applies.
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// tested on the normal BG palette and applies there
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// tested on the normal BG palette and applies there
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//
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//
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// oh also, changing DISPCNT bit16-17 midframe doesn't work (ignored? applied for next frame?)
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// TODO, eventually: check whether other DISPCNT bits can be changed midframe
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//
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// for VRAM display mode, VRAM must be mapped to LCDC
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// for VRAM display mode, VRAM must be mapped to LCDC
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//
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//
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// FIFO display mode:
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// FIFO display mode:
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@ -78,7 +75,10 @@
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// * for rotscaled sprites: coordinates that are inside the sprite are clamped to the sprite region
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// * for rotscaled sprites: coordinates that are inside the sprite are clamped to the sprite region
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// after being transformed for mosaic
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// after being transformed for mosaic
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// TODO: find which parts of DISPCNT are latched. for example, not possible to change video mode midframe.
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// TODO: master brightness, display capture and mainmem FIFO are separate circuitry, distinct from
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// the tile renderers.
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// for example these aren't affected by POWCNT GPU-disable bits.
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// to model the hardware more accurately, the relevant logic should be moved to GPU.cpp.
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GPU2D::GPU2D(u32 num)
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GPU2D::GPU2D(u32 num)
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@ -309,8 +309,6 @@ u32 GPU2D::Read32(u32 addr)
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void GPU2D::Write8(u32 addr, u8 val)
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void GPU2D::Write8(u32 addr, u8 val)
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{
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{
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if (!Enabled) return;
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switch (addr & 0x00000FFF)
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switch (addr & 0x00000FFF)
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{
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{
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case 0x000:
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case 0x000:
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@ -329,7 +327,12 @@ void GPU2D::Write8(u32 addr, u8 val)
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DispCnt = (DispCnt & 0x00FFFFFF) | (val << 24);
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DispCnt = (DispCnt & 0x00FFFFFF) | (val << 24);
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if (Num) DispCnt &= 0xC0B1FFF7;
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if (Num) DispCnt &= 0xC0B1FFF7;
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return;
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return;
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}
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if (!Enabled) return;
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switch (addr & 0x00000FFF)
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{
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case 0x008: BGCnt[0] = (BGCnt[0] & 0xFF00) | val; return;
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case 0x008: BGCnt[0] = (BGCnt[0] & 0xFF00) | val; return;
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case 0x009: BGCnt[0] = (BGCnt[0] & 0x00FF) | (val << 8); return;
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case 0x009: BGCnt[0] = (BGCnt[0] & 0x00FF) | (val << 8); return;
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case 0x00A: BGCnt[1] = (BGCnt[1] & 0xFF00) | val; return;
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case 0x00A: BGCnt[1] = (BGCnt[1] & 0xFF00) | val; return;
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@ -405,8 +408,6 @@ void GPU2D::Write8(u32 addr, u8 val)
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void GPU2D::Write16(u32 addr, u16 val)
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void GPU2D::Write16(u32 addr, u16 val)
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{
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{
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if (!Enabled) return;
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switch (addr & 0x00000FFF)
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switch (addr & 0x00000FFF)
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{
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{
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case 0x000:
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case 0x000:
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@ -418,6 +419,22 @@ void GPU2D::Write16(u32 addr, u16 val)
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if (Num) DispCnt &= 0xC0B1FFF7;
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if (Num) DispCnt &= 0xC0B1FFF7;
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return;
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return;
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case 0x068:
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DispFIFO[DispFIFOWritePtr] = val;
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return;
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case 0x06A:
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DispFIFO[DispFIFOWritePtr+1] = val;
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DispFIFOWritePtr += 2;
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DispFIFOWritePtr &= 0xF;
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return;
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case 0x06C: MasterBrightness = val; return;
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}
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if (!Enabled) return;
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switch (addr & 0x00000FFF)
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{
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case 0x008: BGCnt[0] = val; return;
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case 0x008: BGCnt[0] = val; return;
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case 0x00A: BGCnt[1] = val; return;
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case 0x00A: BGCnt[1] = val; return;
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case 0x00C: BGCnt[2] = val; return;
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case 0x00C: BGCnt[2] = val; return;
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@ -526,17 +543,6 @@ void GPU2D::Write16(u32 addr, u16 val)
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EVY = val & 0x1F;
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EVY = val & 0x1F;
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if (EVY > 16) EVY = 16;
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if (EVY > 16) EVY = 16;
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return;
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return;
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case 0x068:
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DispFIFO[DispFIFOWritePtr] = val;
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return;
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case 0x06A:
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DispFIFO[DispFIFOWritePtr+1] = val;
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DispFIFOWritePtr += 2;
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DispFIFOWritePtr &= 0xF;
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return;
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case 0x06C: MasterBrightness = val; return;
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}
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}
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//printf("unknown GPU write16 %08X %04X\n", addr, val);
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//printf("unknown GPU write16 %08X %04X\n", addr, val);
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@ -544,8 +550,6 @@ void GPU2D::Write16(u32 addr, u16 val)
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void GPU2D::Write32(u32 addr, u32 val)
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void GPU2D::Write32(u32 addr, u32 val)
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{
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{
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if (!Enabled) return;
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switch (addr & 0x00000FFF)
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switch (addr & 0x00000FFF)
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{
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{
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case 0x000:
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case 0x000:
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@ -553,6 +557,24 @@ void GPU2D::Write32(u32 addr, u32 val)
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if (Num) DispCnt &= 0xC0B1FFF7;
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if (Num) DispCnt &= 0xC0B1FFF7;
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return;
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return;
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case 0x064:
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// TODO: check what happens when writing to it during display
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// esp. if a capture is happening
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CaptureCnt = val & 0xEF3F1F1F;
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return;
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case 0x068:
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DispFIFO[DispFIFOWritePtr] = val & 0xFFFF;
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DispFIFO[DispFIFOWritePtr+1] = val >> 16;
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DispFIFOWritePtr += 2;
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DispFIFOWritePtr &= 0xF;
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return;
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}
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if (!Enabled) return;
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switch (addr & 0x00000FFF)
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{
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case 0x028:
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case 0x028:
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if (val & 0x08000000) val |= 0xF0000000;
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if (val & 0x08000000) val |= 0xF0000000;
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BGXRef[0] = val;
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BGXRef[0] = val;
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@ -574,19 +596,6 @@ void GPU2D::Write32(u32 addr, u32 val)
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BGYRef[1] = val;
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BGYRef[1] = val;
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if (GPU::VCount < 192) BGYRefInternal[1] = BGYRef[1];
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if (GPU::VCount < 192) BGYRefInternal[1] = BGYRef[1];
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return;
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return;
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case 0x064:
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// TODO: check what happens when writing to it during display
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// esp. if a capture is happening
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CaptureCnt = val & 0xEF3F1F1F;
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return;
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case 0x068:
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DispFIFO[DispFIFOWritePtr] = val & 0xFFFF;
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DispFIFO[DispFIFOWritePtr+1] = val >> 16;
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DispFIFOWritePtr += 2;
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DispFIFOWritePtr &= 0xF;
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return;
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}
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}
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Write16(addr, val&0xFFFF);
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Write16(addr, val&0xFFFF);
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