diff --git a/ARM.cpp b/ARM.cpp
index 3166fb85..8a5c6bb3 100644
--- a/ARM.cpp
+++ b/ARM.cpp
@@ -290,6 +290,40 @@ s32 ARM::Execute(s32 cycles)
                 TriggerIRQ();
         }
 
+        // R1=X R2=Y
+        //if (R[15]==0x02328E88)
+        //    printf("hah! %04X %08X %08X %08X\n", Read16(R[0]+4), R[1], R[2],
+        //           Read32(R[13]+0x18+16+4));
+        /*if (R[15]==0x02328DA6)
+            printf("derpo %08X %08X %08X %08X %08X %08X | %08X\n", R[0], R[1], R[2], R[3],
+               Read32(R[13]+0x40+0), Read32(R[13]+0x40+4), R[14]);*/
+
+        /*if (R[15]==0x02328C64)
+            printf("derpo %08X %08X %08X %08X %08X %08X %08X %08X | %08X | %04X %04X\n", R[0], R[1], R[2], R[3],
+               Read32(R[13]+0x40+0), Read32(R[13]+0x40+4), Read32(R[13]+0x40+8), Read32(R[13]+0x40+12), R[14],
+                Read16(R[0]+8), Read16(R[0]+12));*/
+
+        /*if (R[15]==0x023290B2)
+            printf("derpo %08X %08X %08X %08X | %08X\n", R[0], R[1], R[2], R[3],
+               R[14]);
+
+        if (R[15]==0x23290DE)
+            printf("!!!!! %08X %04X %04X %08X  %08X %08X %08X\n", R[3], Read16(R[3]), Read16(R[3]+2), R[2],
+                   Read32(0x023A6184+0), Read32(0x023A6184+4), Read32(0x023A6184+8));
+        if (R[15]==0x23290EA)
+            printf("!!!!! %08X %08X\n", R[2], R[3]);
+
+        if (R[15]==0x2328C80)
+            printf("STRING SIZE=%08X\n", R[0]);
+        if (R[15]==0x2328CC2)
+            printf("SUMLOL=%08X %08X %08X\n", R[4], R[7], R[0]);
+        if (R[15]==0x2328CC8)
+            printf("SUM=%08X %08X %08X\n", R[4], R[7], R[0]);
+        if (R[15]>=0x2328D6C && R[15]<=0x2328D9C)
+            printf("%08X CALC %08X %08X\n", R[15]-4, R[0], R[1]);
+        if (R[15]>=0x232CCCC && R[15]<=0x232CED4)
+            printf("%08X DIV %08X %08X %08X %08X carry %d\n", R[15]-4, R[0], R[1], R[2], R[3], (CPSR&0x20000000)?1:0);*/
+
         // temp. debug cruft
         addr = R[15] - (CPSR&0x20 ? 4:8);
         cpsr = CPSR;
diff --git a/ARMInterpreter_ALU.cpp b/ARMInterpreter_ALU.cpp
index d38cb947..702c1c8c 100644
--- a/ARMInterpreter_ALU.cpp
+++ b/ARMInterpreter_ALU.cpp
@@ -137,7 +137,7 @@ namespace ARMInterpreter
     shiftop(b, cpu->R[(cpu->CurInstr>>8)&0xF]);
 
 
-#define A_IMPLEMENT_ALU_OP(x) \
+#define A_IMPLEMENT_ALU_OP(x,s) \
 \
 s32 A_##x##_IMM(ARM* cpu) \
 { \
@@ -191,46 +191,46 @@ s32 A_##x##_IMM_S(ARM* cpu) \
 } \
 s32 A_##x##_REG_LSL_IMM_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM##s) \
     A_##x##_S(0) \
 } \
 s32 A_##x##_REG_LSR_IMM_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM##s) \
     A_##x##_S(0) \
 } \
 s32 A_##x##_REG_ASR_IMM_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM##s) \
     A_##x##_S(0) \
 } \
 s32 A_##x##_REG_ROR_IMM_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM##s) \
     A_##x##_S(0) \
 } \
 s32 A_##x##_REG_LSL_REG_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(LSL_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(LSL_REG##s) \
     A_##x##_S(1) \
 } \
 s32 A_##x##_REG_LSR_REG_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(LSR_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(LSR_REG##s) \
     A_##x##_S(1) \
 } \
 s32 A_##x##_REG_ASR_REG_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(ASR_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(ASR_REG##s) \
     A_##x##_S(1) \
 } \
 s32 A_##x##_REG_ROR_REG_S(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(ROR_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(ROR_REG##s) \
     A_##x##_S(1) \
 }
 
-#define A_IMPLEMENT_ALU_TEST(x) \
+#define A_IMPLEMENT_ALU_TEST(x,s) \
 \
 s32 A_##x##_IMM(ARM* cpu) \
 { \
@@ -239,42 +239,42 @@ s32 A_##x##_IMM(ARM* cpu) \
 } \
 s32 A_##x##_REG_LSL_IMM(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(LSL_IMM##s) \
     A_##x(0) \
 } \
 s32 A_##x##_REG_LSR_IMM(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(LSR_IMM##s) \
     A_##x(0) \
 } \
 s32 A_##x##_REG_ASR_IMM(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(ASR_IMM##s) \
     A_##x(0) \
 } \
 s32 A_##x##_REG_ROR_IMM(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM_S) \
+    A_CALC_OP2_REG_SHIFT_IMM(ROR_IMM##s) \
     A_##x(0) \
 } \
 s32 A_##x##_REG_LSL_REG(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(LSL_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(LSL_REG##s) \
     A_##x(1) \
 } \
 s32 A_##x##_REG_LSR_REG(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(LSR_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(LSR_REG##s) \
     A_##x(1) \
 } \
 s32 A_##x##_REG_ASR_REG(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(ASR_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(ASR_REG##s) \
     A_##x(1) \
 } \
 s32 A_##x##_REG_ROR_REG(ARM* cpu) \
 { \
-    A_CALC_OP2_REG_SHIFT_REG(ROR_REG_S) \
+    A_CALC_OP2_REG_SHIFT_REG(ROR_REG##s) \
     A_##x(1) \
 }
 
@@ -309,7 +309,7 @@ s32 A_##x##_REG_ROR_REG(ARM* cpu) \
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(AND)
+A_IMPLEMENT_ALU_OP(AND,_S)
 
 
 #define A_EOR(c) \
@@ -342,7 +342,7 @@ A_IMPLEMENT_ALU_OP(AND)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(EOR)
+A_IMPLEMENT_ALU_OP(EOR,_S)
 
 
 #define A_SUB(c) \
@@ -377,7 +377,7 @@ A_IMPLEMENT_ALU_OP(EOR)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(SUB)
+A_IMPLEMENT_ALU_OP(SUB,)
 
 
 #define A_RSB(c) \
@@ -412,7 +412,7 @@ A_IMPLEMENT_ALU_OP(SUB)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(RSB)
+A_IMPLEMENT_ALU_OP(RSB,)
 
 
 #define A_ADD(c) \
@@ -447,7 +447,7 @@ A_IMPLEMENT_ALU_OP(RSB)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(ADD)
+A_IMPLEMENT_ALU_OP(ADD,)
 
 
 #define A_ADC(c) \
@@ -484,7 +484,7 @@ A_IMPLEMENT_ALU_OP(ADD)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(ADC)
+A_IMPLEMENT_ALU_OP(ADC,)
 
 
 #define A_SBC(c) \
@@ -521,7 +521,7 @@ A_IMPLEMENT_ALU_OP(ADC)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(SBC)
+A_IMPLEMENT_ALU_OP(SBC,)
 
 
 #define A_RSC(c) \
@@ -558,7 +558,7 @@ A_IMPLEMENT_ALU_OP(SBC)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(RSC)
+A_IMPLEMENT_ALU_OP(RSC,)
 
 
 #define A_TST(c) \
@@ -568,7 +568,7 @@ A_IMPLEMENT_ALU_OP(RSC)
                !res); \
     return C_S(1) + C_I(c);
 
-A_IMPLEMENT_ALU_TEST(TST)
+A_IMPLEMENT_ALU_TEST(TST,_S)
 
 
 #define A_TEQ(c) \
@@ -578,7 +578,7 @@ A_IMPLEMENT_ALU_TEST(TST)
                !res); \
     return C_S(1) + C_I(c);
 
-A_IMPLEMENT_ALU_TEST(TEQ)
+A_IMPLEMENT_ALU_TEST(TEQ,_S)
 
 
 #define A_CMP(c) \
@@ -590,7 +590,7 @@ A_IMPLEMENT_ALU_TEST(TEQ)
                  OVERFLOW_SUB(a, b, res)); \
     return C_S(1) + C_I(c);
 
-A_IMPLEMENT_ALU_TEST(CMP)
+A_IMPLEMENT_ALU_TEST(CMP,)
 
 
 #define A_CMN(c) \
@@ -602,7 +602,7 @@ A_IMPLEMENT_ALU_TEST(CMP)
                  OVERFLOW_ADD(a, b, res)); \
     return C_S(1) + C_I(c);
 
-A_IMPLEMENT_ALU_TEST(CMN)
+A_IMPLEMENT_ALU_TEST(CMN,)
 
 
 #define A_ORR(c) \
@@ -635,7 +635,7 @@ A_IMPLEMENT_ALU_TEST(CMN)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(ORR)
+A_IMPLEMENT_ALU_OP(ORR,_S)
 
 
 #define A_MOV(c) \
@@ -664,7 +664,7 @@ A_IMPLEMENT_ALU_OP(ORR)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(MOV)
+A_IMPLEMENT_ALU_OP(MOV,_S)
 
 
 #define A_BIC(c) \
@@ -697,7 +697,7 @@ A_IMPLEMENT_ALU_OP(MOV)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(BIC)
+A_IMPLEMENT_ALU_OP(BIC,_S)
 
 
 #define A_MVN(c) \
@@ -728,7 +728,7 @@ A_IMPLEMENT_ALU_OP(BIC)
         return C_S(1) + C_I(c); \
     }
 
-A_IMPLEMENT_ALU_OP(MVN)
+A_IMPLEMENT_ALU_OP(MVN,_S)
 
 
 
diff --git a/DMA.cpp b/DMA.cpp
index cd7bf4d6..59bac48e 100644
--- a/DMA.cpp
+++ b/DMA.cpp
@@ -106,7 +106,7 @@ void DMA::Start()
     if ((Cnt & 0x00060000) == 0x00060000)
         CurDstAddr = DstAddr;
 
-    //printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt & 0x04000000)?2:4), (Cnt & 0x04000000)?16:32);
+    //printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt&0x04000000)?4:2), (Cnt&0x04000000)?32:16);
 
     // TODO: NOT MAKE THE DMA INSTANT!!
     if (!(Cnt & 0x04000000))
diff --git a/GPU2D.cpp b/GPU2D.cpp
index 12ed1667..819d4eae 100644
--- a/GPU2D.cpp
+++ b/GPU2D.cpp
@@ -89,11 +89,11 @@ void GPU2D::Write16(u32 addr, u16 val)
     {
     case 0x000:
         DispCnt = (DispCnt & 0xFFFF0000) | val;
-        printf("[L] DISPCNT=%08X\n", DispCnt);
+        //printf("[L] DISPCNT=%08X\n", DispCnt);
         return;
     case 0x002:
         DispCnt = (DispCnt & 0x0000FFFF) | (val << 16);
-        printf("[H] DISPCNT=%08X\n", DispCnt);
+        //printf("[H] DISPCNT=%08X\n", DispCnt);
         return;
 
     case 0x008: BGCnt[0] = val; return;
@@ -110,7 +110,7 @@ void GPU2D::Write32(u32 addr, u32 val)
     switch (addr & 0x00000FFF)
     {
     case 0x000:
-        printf("DISPCNT=%08X\n", val);
+        //printf("DISPCNT=%08X\n", val);
         DispCnt = val;
         return;
     }
@@ -222,7 +222,7 @@ void GPU2D::DrawBG_Text_4bpp(u32 line, u16* dst, u32 bgnum)
 
     if (Num)
     {
-        tileset = (u8*)GPU::VRAM_BBG[((bgcnt & 0x000C) >> 2)];
+        tileset = (u8*)GPU::VRAM_BBG[((bgcnt & 0x003C) >> 2)];
         tilemap = (u16*)GPU::VRAM_BBG[((bgcnt & 0x1800) >> 11)];
         tilemap += ((bgcnt & 0x0700) << 2);
 
@@ -284,6 +284,7 @@ void GPU2D::DrawBG_Text_4bpp(u32 line, u16* dst, u32 bgnum)
         }
         //color = (i >> 4) + ((line >> 4) << 4);
         //if (Num) color = 0;
+        //if (yoff>127) color=0;
         if (color)
             dst[i] = curpal[color];
 
diff --git a/NDS.cpp b/NDS.cpp
index 8a7a8840..68dbf321 100644
--- a/NDS.cpp
+++ b/NDS.cpp
@@ -38,8 +38,10 @@ namespace SPI_Firmware
 namespace NDS
 {
 
-// TODO: stick all the variables in a big structure?
-// would make it easier to deal with savestates
+// TODO LIST
+// * stick all the variables in a big structure?
+//   would make it easier to deal with savestates
+// * move ARM9 TCM to the ARM class (closer to the real thing, and handles "DMA can't access TCM" nicely)
 
 SchedEvent SchedBuffer[SCHED_BUF_LEN];
 SchedEvent* SchedQueue;
@@ -139,8 +141,8 @@ void LoadROM()
 {
     FILE* f;
 
-    //f = fopen("rom/armwrestler.nds", "rb");
-    f = fopen("rom/zorp.nds", "rb");
+    f = fopen("rom/armwrestler.nds", "rb");
+    //f = fopen("rom/zorp.nds", "rb");
 
     u32 bootparams[8];
     fseek(f, 0x20, SEEK_SET);
@@ -968,6 +970,13 @@ void ARM9Write8(u32 addr, u8 val)
 void ARM9Write16(u32 addr, u16 val)
 {
     if (addr == ARM9->R[15]) printf("!!!!!!!!!!!!9999 %08X %04X\n", addr, val);
+    if (addr == 0x02331B44) printf("!! PAL !! %04X %08X\n", val, ARM9->R[15]);
+    /*if (addr >= 0x06218000 && addr < 0x06218000+0x6000 && val)
+    {
+        printf("WRITE TO LAME VRAM %08X %04X %08X, %08X %08X, %08X\n", addr, val, ARM9->R[15], ARM9->R[4], ARM9->R[3],
+               ARM9Read32(ARM9->R[13]+12));
+        //Halt();
+    }*/
     if (addr < ARM9ITCMSize)
     {
         *(u16*)&ARM9ITCM[addr & 0x7FFF] = val;
@@ -1026,6 +1035,7 @@ void ARM9Write32(u32 addr, u32 val)
 {
     if (addr == ARM9->R[15]) printf("!!!!!!!!!!!!9999 %08X %08X\n", addr, val);
     if (addr == 0x023549F0) printf("%08X STATE=%08X\n", ARM9->R[15], val);
+    if (addr == 0x02331B44) printf("!! PAL !! %04X %08X  %08X\n", val, ARM9->R[15], ARM9Read32(0x23312E8));
     if (addr < ARM9ITCMSize)
     {
         *(u32*)&ARM9ITCM[addr & 0x7FFF] = val;
diff --git a/main.cpp b/main.cpp
index 8e40f891..76700e6c 100644
--- a/main.cpp
+++ b/main.cpp
@@ -35,9 +35,10 @@ LRESULT CALLBACK derpo(HWND window, UINT msg, WPARAM wparam, LPARAM lparam)
     case WM_CLOSE:
         printf("close\n");
         {
-            FILE* f = fopen("vram.bin", "wb");
+            // 6006800 6008000
+            FILE* f = fopen("vramABG.bin", "wb");
             for (int i = 0; i < 128; i++)
-                fwrite(GPU::VRAM_BBG[i], 16384, 1, f);
+                fwrite(GPU::VRAM_ABG[i], 16384, 1, f);
             fclose(f);
         }
         PostQuitMessage(0);
diff --git a/melonDS.depend b/melonDS.depend
index 7b5eeb1c..89df6a07 100644
--- a/melonDS.depend
+++ b/melonDS.depend
@@ -1,5 +1,5 @@
 # depslib dependency file v1.0
-1484751556 source:c:\documents\sources\melonds\main.cpp
+1484878707 source:c:\documents\sources\melonds\main.cpp
 	<stdio.h>
 	<windows.h>
 	"NDS.h"
@@ -10,7 +10,7 @@
 
 1481161027 c:\documents\sources\melonds\types.h
 
-1484868036 source:c:\documents\sources\melonds\nds.cpp
+1484919120 source:c:\documents\sources\melonds\nds.cpp
 	<stdio.h>
 	<string.h>
 	"NDS.h"
@@ -23,7 +23,7 @@
 	"RTC.h"
 	"Wifi.h"
 
-1484870885 source:c:\documents\sources\melonds\arm.cpp
+1484917677 source:c:\documents\sources\melonds\arm.cpp
 	<stdio.h>
 	"NDS.h"
 	"ARM.h"
@@ -57,7 +57,7 @@
 
 1481160920 c:\documents\sources\melonds\arminterpreter_alu.h
 
-1481202027 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
+1484917510 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
 	<stdio.h>
 	"ARM.h"
 
@@ -83,7 +83,7 @@
 	"NDS.h"
 	"SPI.h"
 
-1484870914 source:c:\documents\sources\melonds\gpu2d.cpp
+1484920777 source:c:\documents\sources\melonds\gpu2d.cpp
 	<stdio.h>
 	<string.h>
 	"NDS.h"
@@ -105,7 +105,7 @@
 1484612398 c:\documents\sources\melonds\fifo.h
 	"types.h"
 
-1484762586 source:c:\documents\sources\melonds\dma.cpp
+1484871851 source:c:\documents\sources\melonds\dma.cpp
 	<stdio.h>
 	"NDS.h"
 	"DMA.h"