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integrate changes from ARM64 backend and more

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- better handle LDM/STM in reg alloc
- unify Halted and IRQ in anticipation for branch inlining
- literal optimisations can be disabled in gui
- jit blocks follow simple returns
- fix idle loop detection
- break jit blocks on IRQ (fixes saving in Pokemon White)
This commit is contained in:
RSDuck
2019-10-18 13:29:17 +02:00
parent aa23f21b8d
commit 81f38c14be
13 changed files with 179 additions and 48 deletions
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7
src/ARMJIT_x64/ARMJIT_Compiler.cpp
View File

@ -364,7 +364,7 @@ void Compiler::Reset()
void Compiler::Comp_SpecialBranchBehaviour()
{
if (CurInstr.BranchFlags & branch_IdleBranch)
OR(32, MDisp(RCPU, offsetof(ARM, Halted)), Imm8(0x20));
OR(32, MDisp(RCPU, offsetof(ARM, IdleLoop)), Imm8(0x1));
if (CurInstr.BranchFlags & branch_FollowCondNotTaken)
{
@ -402,6 +402,7 @@ JitBlockEntry Compiler::CompileBlock(ARM* cpu, bool thumb, FetchedInstr instrs[]
{
CurInstr = instrs[i];
R15 = CurInstr.Addr + (Thumb ? 4 : 8);
CodeRegion = R15 >> 24;
Exit = i == instrsCount - 1 || (CurInstr.BranchFlags & branch_FollowCondNotTaken);
@ -571,8 +572,6 @@ void Compiler::Comp_AddCycles_CDI()
Comp_AddCycles_CD();
else
{
IrregularCycles = true;
s32 cycles;
s32 numC = NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
@ -642,7 +641,7 @@ void Compiler::Comp_AddCycles_CD()
IrregularCycles = true;
}
if (!Thumb && CurInstr.Cond() < 0xE)
if (IrregularCycles && !Thumb && CurInstr.Cond() < 0xE)
ADD(32, MDisp(RCPU, offsetof(ARM, Cycles)), Imm8(cycles));
else
ConstantCycles += cycles;

16
src/ARMJIT_x64/ARMJIT_LoadStore.cpp
View File

@ -1,5 +1,6 @@
#include "ARMJIT_Compiler.h"
#include "../Config.h"
using namespace Gen;
@ -290,7 +291,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, const ComplexOperand& op2, int siz
if (size == 16)
addressMask = ~1;
if (rn == 15 && rd != 15 && op2.IsImm && !(flags & (memop_SignExtend|memop_Post|memop_Store|memop_Writeback)))
if (Config::JIT_LiteralOptimisations && rn == 15 && rd != 15 && op2.IsImm && !(flags & (memop_SignExtend|memop_Post|memop_Store|memop_Writeback)))
{
u32 addr = R15 + op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1);
Comp_MemLoadLiteral(size, rd, addr);
@ -309,6 +310,8 @@ void Compiler::Comp_MemAccess(int rd, int rn, const ComplexOperand& op2, int siz
OpArg rdMapped = MapReg(rd);
OpArg rnMapped = MapReg(rn);
if (Thumb && rn == 15)
rnMapped = Imm32(R15 & ~0x2);
bool inlinePreparation = Num == 1;
u32 constLocalROR32 = 4;
@ -317,7 +320,7 @@ void Compiler::Comp_MemAccess(int rd, int rn, const ComplexOperand& op2, int siz
? MemoryFuncs9[size >> 4][!!(flags & memop_Store)]
: MemoryFuncs7[size >> 4][!!((flags & memop_Store))];
if ((rd != 15 || (flags & memop_Store)) && op2.IsImm && RegCache.IsLiteral(rn))
if (Config::JIT_LiteralOptimisations && (rd != 15 || (flags & memop_Store)) && op2.IsImm && RegCache.IsLiteral(rn))
{
u32 addr = RegCache.LiteralValues[rn] + op2.Imm * ((flags & memop_SubtractOffset) ? -1 : 1);
@ -749,9 +752,12 @@ void Compiler::T_Comp_MemImmHalf()
void Compiler::T_Comp_LoadPCRel()
{
u32 addr = (R15 & ~0x2) + ((CurInstr.Instr & 0xFF) << 2);
Comp_MemLoadLiteral(32, CurInstr.T_Reg(8), addr);
u32 offset = (CurInstr.Instr & 0xFF) << 2;
u32 addr = (R15 & ~0x2) + offset;
if (Config::JIT_LiteralOptimisations)
Comp_MemLoadLiteral(32, CurInstr.T_Reg(8), addr);
else
Comp_MemAccess(CurInstr.T_Reg(8), 15, ComplexOperand(offset), 32, 0);
}
void Compiler::T_Comp_MemSPRel()