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jit: branch instructions
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@ -22,19 +22,6 @@ class Compiler;
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typedef void (Compiler::*CompileFunc)();
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enum DataRegion
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{
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dataRegionGeneric, // hey, that's me!
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dataRegionMainRAM,
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dataRegionSWRAM,
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dataRegionVRAM,
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dataRegionIO,
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dataRegionExclusive,
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dataRegionsCount,
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dataRegionDTCM = dataRegionExclusive,
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dataRegionWRAM7 = dataRegionExclusive,
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};
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class Compiler : public Gen::X64CodeBlock
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{
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public:
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@ -49,8 +36,9 @@ private:
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CompileFunc GetCompFunc(int kind);
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void Comp_JumpTo(Gen::X64Reg addr, bool restoreCPSR = false);
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void Comp_JumpTo(u32 addr, bool forceNonConstantCycles = false);
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void Comp_AddCycles_C();
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void Comp_AddCycles_C(bool forceNonConstant = false);
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void Comp_AddCycles_CI(u32 i);
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enum
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@ -63,8 +51,6 @@ private:
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opInvertOp2 = 1 << 5,
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};
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DataRegion ClassifyAddress(u32 addr);
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void A_Comp_Arith();
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void A_Comp_MovOp();
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void A_Comp_CmpOp();
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@ -73,6 +59,9 @@ private:
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void A_Comp_MemHalf();
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void A_Comp_LDM_STM();
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void A_Comp_BranchImm();
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void A_Comp_BranchXchangeReg();
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void T_Comp_ShiftImm();
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void T_Comp_AddSub_();
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void T_Comp_ALU_Imm8();
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@ -91,6 +80,13 @@ private:
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void T_Comp_PUSH_POP();
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void T_Comp_LDMIA_STMIA();
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void T_Comp_BCOND();
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void T_Comp_B();
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void T_Comp_BranchXchangeReg();
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void T_Comp_BL_LONG_1();
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void T_Comp_BL_LONG_2();
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void T_Comp_BL_Merged(FetchedInstr prefix);
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void Comp_MemAccess(Gen::OpArg rd, bool signExtend, bool store, int size);
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s32 Comp_MemAccessBlock(Gen::OpArg rb, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode);
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@ -119,6 +115,8 @@ private:
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void LoadCPSR();
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void SaveCPSR();
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Gen::FixupBranch CheckCondition(u32 cond);
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Gen::OpArg MapReg(int reg)
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{
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if (reg == 15 && RegCache.Mapping[reg] == Gen::INVALID_REG)
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