add MSR/MRS. also fix misc error with LDR ROR effect.

see shibboleet, I can do it too :>
This commit is contained in:
StapleButter
2016-12-03 02:09:04 +01:00
parent 23d584ca4c
commit 844ca45055
5 changed files with 113 additions and 16 deletions

View File

@ -8,6 +8,10 @@
namespace ARMInterpreter
{
s32 A_MSR_IMM(ARM* cpu);
s32 A_MSR_REG(ARM* cpu);
s32 A_MRS(ARM* cpu);
extern s32 (*ARMInstrTable[4096])(ARM* cpu);
extern s32 (*THUMBInstrTable[1024])(ARM* cpu);