mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 14:19:55 -06:00
make this other branch where we're going to actually make it usable
but it'll be a gross hack
This commit is contained in:
StapleButter
333
src/CP15.cpp
333
src/CP15.cpp
@ -25,7 +25,7 @@
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void ARMv5::CP15Reset()
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{
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CP15Control = 0x78; // dunno
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CP15Control = 0x2078; // dunno
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DTCMSetting = 0;
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ITCMSetting = 0;
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@ -36,6 +36,16 @@ void ARMv5::CP15Reset()
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ITCMSize = 0;
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DTCMBase = 0xFFFFFFFF;
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DTCMSize = 0;
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PU_CodeCacheable = 0;
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PU_DataCacheable = 0;
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PU_DataCacheWrite = 0;
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PU_CodeRW = 0;
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PU_DataRW = 0;
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memset(PU_Region, 0, 8*sizeof(u32));
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UpdatePURegions();
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}
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void ARMv5::CP15DoSavestate(Savestate* file)
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@ -64,13 +74,13 @@ void ARMv5::UpdateDTCMSetting()
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{
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DTCMBase = DTCMSetting & 0xFFFFF000;
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DTCMSize = 0x200 << ((DTCMSetting >> 1) & 0x1F);
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//printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, DTCMBase, DTCMSize);
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printf("DTCM [%08X] enabled at %08X, size %X\n", DTCMSetting, DTCMBase, DTCMSize);
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}
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else
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{
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DTCMBase = 0xFFFFFFFF;
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DTCMSize = 0;
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//printf("DTCM disabled\n");
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printf("DTCM disabled\n");
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}
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}
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@ -79,12 +89,128 @@ void ARMv5::UpdateITCMSetting()
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if (CP15Control & (1<<18))
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{
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ITCMSize = 0x200 << ((ITCMSetting >> 1) & 0x1F);
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//printf("ITCM [%08X] enabled at %08X, size %X\n", ITCMSetting, 0, ITCMSize);
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printf("ITCM [%08X] enabled at %08X, size %X\n", ITCMSetting, 0, ITCMSize);
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}
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else
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{
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ITCMSize = 0;
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//printf("ITCM disabled\n");
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printf("ITCM disabled\n");
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}
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}
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void ARMv5::UpdatePURegions()
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{
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if (!(CP15Control & (1<<0)))
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{
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// PU disabled
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u8 mask = 0x07;
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if (CP15Control & (1<<2)) mask |= 0x30;
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if (CP15Control & (1<<12)) mask |= 0x40;
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memset(PU_UserMap, mask, 0x100000);
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memset(PU_PrivMap, mask, 0x100000);
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return;
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}
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memset(PU_UserMap, 0, 0x100000);
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memset(PU_PrivMap, 0, 0x100000);
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u32 coderw = PU_CodeRW;
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u32 datarw = PU_DataRW;
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u32 codecache, datacache, datawrite;
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// datacache/datawrite
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// 0/0: goes to memory
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// 0/1: goes to memory
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// 1/0: goes to memory and cache
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// 1/1: goes to cache
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if (CP15Control & (1<<12))
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codecache = PU_CodeCacheable;
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else
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codecache = 0;
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if (CP15Control & (1<<2))
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{
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datacache = PU_DataCacheable;
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datawrite = PU_DataCacheWrite;
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}
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else
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{
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datacache = 0;
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datawrite = 0;
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}
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for (int n = 0; n < 8; n++)
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{
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u32 rgn = PU_Region[n];
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if (!(rgn & (1<<0))) continue;
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u32 start = rgn >> 12;
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u32 sz = 2 << ((rgn >> 1) & 0x1F);
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u32 end = start + (sz >> 12);
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// TODO: check alignment of start
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u8 usermask = 0;
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u8 privmask = 0;
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switch (datarw & 0xF)
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{
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case 0: break;
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case 1: privmask |= 0x03; break;
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case 2: privmask |= 0x03; usermask |= 0x01; break;
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case 3: privmask |= 0x03; usermask |= 0x03; break;
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case 5: privmask |= 0x01; break;
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case 6: privmask |= 0x01; usermask |= 0x01; break;
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default: printf("!! BAD DATARW VALUE %d\n", datarw&0xF);
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}
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switch (coderw & 0xF)
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{
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case 0: break;
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case 1: privmask |= 0x04; break;
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case 2: privmask |= 0x04; usermask |= 0x04; break;
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case 3: privmask |= 0x04; usermask |= 0x04; break;
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case 5: privmask |= 0x04; break;
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case 6: privmask |= 0x04; usermask |= 0x04; break;
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default: printf("!! BAD CODERW VALUE %d\n", datarw&0xF);
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}
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if (datacache & 0x1)
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{
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privmask |= 0x10;
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usermask |= 0x10;
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if (datawrite & 0x1)
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{
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privmask |= 0x20;
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usermask |= 0x20;
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}
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}
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if (codecache & 0x1)
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{
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privmask |= 0x40;
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usermask |= 0x40;
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}
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printf("PU region %d: %08X-%08X, user=%02X priv=%02X\n", n, start<<12, end<<12, usermask, privmask);
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for (u32 i = start; i < end; i++)
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{
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PU_UserMap[i] = usermask;
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PU_PrivMap[i] = privmask;
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}
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coderw >>= 4;
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datarw >>= 4;
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codecache >>= 1;
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datacache >>= 1;
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datawrite >>= 1;
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}
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}
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@ -96,28 +222,39 @@ void ARMv5::CP15Write(u32 id, u32 val)
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switch (id)
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{
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case 0x100:
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val &= 0x000FF085;
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CP15Control &= ~0x000FF085;
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CP15Control |= val;
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UpdateDTCMSetting();
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UpdateITCMSetting();
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{
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u32 old = CP15Control;
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val &= 0x000FF085;
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CP15Control &= ~0x000FF085;
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CP15Control |= val;
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printf("CP15Control = %08X (%08X->%08X)\n", CP15Control, old, val);
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UpdateDTCMSetting();
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UpdateITCMSetting();
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if ((old & 0x1005) != (val & 0x1005)) UpdatePURegions();
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if (val & (1<<7)) printf("!!!! ARM9 BIG ENDIAN MODE. VERY BAD. SHIT GONNA ASPLODE NOW\n");
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if (val & (1<<13)) ExceptionBase = 0xFFFF0000;
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else ExceptionBase = 0x00000000;
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}
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return;
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case 0x200: // data cacheable
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PU_DataCacheable = val;
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printf("PU: DataCacheable=%08X\n", val);
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UpdatePURegions();
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return;
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case 0x201: // code cacheable
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PU_CodeCacheable = val;
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printf("PU: CodeCacheable=%08X\n", val);
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UpdatePURegions();
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return;
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case 0x300: // data cache write-buffer
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PU_DataCacheWrite = val;
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printf("PU: DataCacheWrite=%08X\n", val);
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UpdatePURegions();
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return;
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@ -132,6 +269,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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PU_DataRW |= ((val & 0x3000) << 12);
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PU_DataRW |= ((val & 0xC000) << 14);
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printf("PU: DataRW=%08X (legacy %08X)\n", PU_DataRW, val);
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UpdatePURegions();
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return;
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case 0x501: // legacy code permissions
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@ -145,16 +283,19 @@ void ARMv5::CP15Write(u32 id, u32 val)
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PU_CodeRW |= ((val & 0x3000) << 12);
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PU_CodeRW |= ((val & 0xC000) << 14);
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printf("PU: CodeRW=%08X (legacy %08X)\n", PU_CodeRW, val);
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UpdatePURegions();
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return;
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case 0x502: // data permissions
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PU_DataRW = val;
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printf("PU: DataRW=%08X\n", PU_DataRW);
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UpdatePURegions();
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return;
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case 0x503: // code permissions
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PU_CodeRW = val;
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printf("PU: CodeRW=%08X\n", PU_CodeRW);
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UpdatePURegions();
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return;
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@ -179,6 +320,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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printf("%s, ", val&1 ? "enabled":"disabled");
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printf("%08X-", val&0xFFFFF000);
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printf("%08X\n", (val&0xFFFFF000)+(2<<((val&0x3E)>>1)));
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UpdatePURegions();
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return;
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@ -318,7 +460,7 @@ u32 ARMv5::CP15Read(u32 id)
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u32 ARMv5::CodeRead32(u32 addr)
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{
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// PU/cache check here
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u8 pu = PU_Map[addr>>12];
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if (addr < ITCMSize)
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{
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@ -328,34 +470,49 @@ u32 ARMv5::CodeRead32(u32 addr)
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u32 ret;
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CodeRegion = NDS::ARM9Read32(addr, &ret);
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if (pu & 0x40) CodeRegion = NDS::Region9_ICache;
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return ret;
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}
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bool ARMv5::DataRead8(u32 addr, u32* val, u32 flags)
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{
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// PU/cache check here
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u8 pu = PU_Map[addr>>12];
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/*if (!(pu & 0x01))
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{
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DataAbort();
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return false;
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}*/
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if (addr < ITCMSize)
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{
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DataRegion = NDS::Region9_ITCM;
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DataCycles += 1;
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if (flags & RWFlags_Nonseq) DataCycles = 1;
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else DataCycles += 1;
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*val = *(u8*)&ITCM[addr & 0x7FFF];
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return true;
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}
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if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
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{
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DataRegion = NDS::Region9_ITCM;
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DataCycles += 1;
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DataRegion = NDS::Region9_DTCM;
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if (flags & RWFlags_Nonseq) DataCycles = 1;
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else DataCycles += 1;
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*val = *(u8*)&DTCM[(addr - DTCMBase) & 0x3FFF];
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return true;
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}
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DataRegion = NDS::ARM9Read8(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM9MemTimings[DataRegion][0];
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if (pu & 0x10)
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{
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DataRegion = NDS::Region9_DCache;
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if (flags & RWFlags_Nonseq) DataCycles = 2;
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else DataCycles += 2;
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}
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else
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DataCycles += NDS::ARM9MemTimings[DataRegion][1];
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{
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if (flags & RWFlags_Nonseq) DataCycles = NDS::ARM9MemTimings[DataRegion][0];
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else DataCycles += NDS::ARM9MemTimings[DataRegion][1];
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}
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return true;
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}
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@ -363,28 +520,42 @@ bool ARMv5::DataRead16(u32 addr, u32* val, u32 flags)
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{
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addr &= ~1;
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// PU/cache check here
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u8 pu = PU_Map[addr>>12];
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/*if (!(pu & 0x01))
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{
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DataAbort();
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return false;
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}*/
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if (addr < ITCMSize)
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{
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DataRegion = NDS::Region9_ITCM;
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DataCycles += 1;
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if (flags & RWFlags_Nonseq) DataCycles = 1;
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else DataCycles += 1;
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*val = *(u16*)&ITCM[addr & 0x7FFF];
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return true;
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}
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if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
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{
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DataRegion = NDS::Region9_ITCM;
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DataCycles += 1;
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DataRegion = NDS::Region9_DTCM;
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if (flags & RWFlags_Nonseq) DataCycles = 1;
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else DataCycles += 1;
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*val = *(u16*)&DTCM[(addr - DTCMBase) & 0x3FFF];
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return true;
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}
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DataRegion = NDS::ARM9Read16(addr, val);
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if (flags & RWFlags_Nonseq)
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DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
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if (pu & 0x10)
|
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{
|
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DataRegion = NDS::Region9_DCache;
|
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if (flags & RWFlags_Nonseq) DataCycles = 2;
|
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else DataCycles += 2;
|
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}
|
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else
|
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DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
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{
|
||||
if (flags & RWFlags_Nonseq) DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
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else DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
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}
|
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return true;
|
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}
|
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|
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@ -392,55 +563,83 @@ bool ARMv5::DataRead32(u32 addr, u32* val, u32 flags)
|
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{
|
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addr &= ~3;
|
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|
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// PU/cache check here
|
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u8 pu = PU_Map[addr>>12];
|
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/*if (!(pu & 0x01))
|
||||
{
|
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DataAbort();
|
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return false;
|
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}*/
|
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|
||||
if (addr < ITCMSize)
|
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{
|
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DataRegion = NDS::Region9_ITCM;
|
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DataCycles += 1;
|
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if (flags & RWFlags_Nonseq) DataCycles = 1;
|
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else DataCycles += 1;
|
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*val = *(u32*)&ITCM[addr & 0x7FFF];
|
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return true;
|
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}
|
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if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
|
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{
|
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DataRegion = NDS::Region9_ITCM;
|
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DataCycles += 1;
|
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DataRegion = NDS::Region9_DTCM;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 1;
|
||||
else DataCycles += 1;
|
||||
*val = *(u32*)&DTCM[(addr - DTCMBase) & 0x3FFF];
|
||||
return true;
|
||||
}
|
||||
|
||||
DataRegion = NDS::ARM9Read32(addr, val);
|
||||
if (flags & RWFlags_Nonseq)
|
||||
DataCycles = NDS::ARM9MemTimings[DataRegion][2];
|
||||
if (pu & 0x10)
|
||||
{
|
||||
DataRegion = NDS::Region9_DCache;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 2;
|
||||
else DataCycles += 2;
|
||||
}
|
||||
else
|
||||
DataCycles += NDS::ARM9MemTimings[DataRegion][3];
|
||||
{
|
||||
if (flags & RWFlags_Nonseq) DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
||||
else DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ARMv5::DataWrite8(u32 addr, u8 val, u32 flags)
|
||||
{
|
||||
// PU/cache check here
|
||||
u8 pu = PU_Map[addr>>12];
|
||||
/*if (!(pu & 0x02))
|
||||
{
|
||||
DataAbort();
|
||||
return false;
|
||||
}*/
|
||||
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataRegion = NDS::Region9_ITCM;
|
||||
DataCycles += 1;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 1;
|
||||
else DataCycles += 1;
|
||||
*(u8*)&ITCM[addr & 0x7FFF] = val;
|
||||
return true;
|
||||
}
|
||||
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
|
||||
{
|
||||
DataRegion = NDS::Region9_ITCM;
|
||||
DataCycles += 1;
|
||||
DataRegion = NDS::Region9_DTCM;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 1;
|
||||
else DataCycles += 1;
|
||||
*(u8*)&DTCM[(addr - DTCMBase) & 0x3FFF] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
DataRegion = NDS::ARM9Write8(addr, val);
|
||||
if (flags & RWFlags_Nonseq)
|
||||
DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
||||
if (pu & 0x20)
|
||||
{
|
||||
DataRegion = NDS::Region9_DCache;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 2;
|
||||
else DataCycles += 2;
|
||||
}
|
||||
else
|
||||
DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
||||
{
|
||||
if (flags & RWFlags_Nonseq) DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
||||
else DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -448,28 +647,42 @@ bool ARMv5::DataWrite16(u32 addr, u16 val, u32 flags)
|
||||
{
|
||||
addr &= ~1;
|
||||
|
||||
// PU/cache check here
|
||||
u8 pu = PU_Map[addr>>12];
|
||||
/*if (!(pu & 0x02))
|
||||
{
|
||||
DataAbort();
|
||||
return false;
|
||||
}*/
|
||||
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataRegion = NDS::Region9_ITCM;
|
||||
DataCycles += 1;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 1;
|
||||
else DataCycles += 1;
|
||||
*(u16*)&ITCM[addr & 0x7FFF] = val;
|
||||
return true;
|
||||
}
|
||||
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
|
||||
{
|
||||
DataRegion = NDS::Region9_ITCM;
|
||||
DataCycles += 1;
|
||||
DataRegion = NDS::Region9_DTCM;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 1;
|
||||
else DataCycles += 1;
|
||||
*(u16*)&DTCM[(addr - DTCMBase) & 0x3FFF] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
DataRegion = NDS::ARM9Write16(addr, val);
|
||||
if (flags & RWFlags_Nonseq)
|
||||
DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
||||
if (pu & 0x20)
|
||||
{
|
||||
DataRegion = NDS::Region9_DCache;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 2;
|
||||
else DataCycles += 2;
|
||||
}
|
||||
else
|
||||
DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
||||
{
|
||||
if (flags & RWFlags_Nonseq) DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
||||
else DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -477,28 +690,42 @@ bool ARMv5::DataWrite32(u32 addr, u32 val, u32 flags)
|
||||
{
|
||||
addr &= ~3;
|
||||
|
||||
// PU/cache check here
|
||||
u8 pu = PU_Map[addr>>12];
|
||||
/*if (!(pu & 0x02))
|
||||
{
|
||||
DataAbort();
|
||||
return false;
|
||||
}*/
|
||||
|
||||
if (addr < ITCMSize)
|
||||
{
|
||||
DataRegion = NDS::Region9_ITCM;
|
||||
DataCycles += 1;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 1;
|
||||
else DataCycles += 1;
|
||||
*(u32*)&ITCM[addr & 0x7FFF] = val;
|
||||
return true;
|
||||
}
|
||||
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
|
||||
{
|
||||
DataRegion = NDS::Region9_ITCM;
|
||||
DataCycles += 1;
|
||||
DataRegion = NDS::Region9_DTCM;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 1;
|
||||
else DataCycles += 1;
|
||||
*(u32*)&DTCM[(addr - DTCMBase) & 0x3FFF] = val;
|
||||
return true;
|
||||
}
|
||||
|
||||
DataRegion = NDS::ARM9Write32(addr, val);
|
||||
if (flags & RWFlags_Nonseq)
|
||||
DataCycles = NDS::ARM9MemTimings[DataRegion][2];
|
||||
if (pu & 0x20)
|
||||
{
|
||||
DataRegion = NDS::Region9_DCache;
|
||||
if (flags & RWFlags_Nonseq) DataCycles = 2;
|
||||
else DataCycles += 2;
|
||||
}
|
||||
else
|
||||
DataCycles += NDS::ARM9MemTimings[DataRegion][3];
|
||||
{
|
||||
if (flags & RWFlags_Nonseq) DataCycles = NDS::ARM9MemTimings[DataRegion][0];
|
||||
else DataCycles += NDS::ARM9MemTimings[DataRegion][1];
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user