mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-22 22:01:06 -06:00
Move GBACart-related global state into objects (#1870)
- RAII will now do the heavy lifting - Mark some methods as const or noexcept - Once the `NDS` object is finalized, most of these `assert`s can go away
This commit is contained in:
Jesse Talavera-Greenberg
committed by
GitHub
GitHub
parent
b4ff911fa3
commit
8b47178add
136
src/NDS.cpp
136
src/NDS.cpp
@ -16,6 +16,7 @@
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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@ -182,7 +183,7 @@ class SPU* SPU;
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class SPIHost* SPI;
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class RTC* RTC;
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class Wifi* Wifi;
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std::unique_ptr<GBACart::GBACartSlot> GBACartSlot;
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class AREngine* AREngine;
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bool Running;
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@ -226,9 +227,9 @@ bool Init()
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SPI = new class SPIHost();
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RTC = new class RTC();
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Wifi = new class Wifi();
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GBACartSlot = std::make_unique<GBACart::GBACartSlot>();
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if (!NDSCart::Init()) return false;
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if (!GBACart::Init()) return false;
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if (!GPU::Init()) return false;
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if (!DSi::Init()) return false;
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@ -259,7 +260,7 @@ void DeInit()
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delete Wifi; Wifi = nullptr;
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NDSCart::DeInit();
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GBACart::DeInit();
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GBACartSlot = nullptr;
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GPU::DeInit();
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DSi::DeInit();
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@ -644,7 +645,7 @@ void Reset()
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RCnt = 0;
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NDSCart::Reset();
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GBACart::Reset();
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GBACartSlot->Reset();
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GPU::Reset();
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SPU->Reset();
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SPI->Reset();
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@ -846,7 +847,7 @@ bool DoSavestate(Savestate* file)
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NDSCart::DoSavestate(file);
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if (ConsoleType == 0)
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GBACart::DoSavestate(file);
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GBACartSlot->DoSavestate(file);
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GPU::DoSavestate(file);
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SPU->DoSavestate(file);
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SPI->DoSavestate(file);
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@ -911,23 +912,28 @@ bool CartInserted()
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bool LoadGBACart(const u8* romdata, u32 romlen, const u8* savedata, u32 savelen)
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{
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if (!GBACart::LoadROM(romdata, romlen))
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if (!GBACartSlot)
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return false;
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if (!GBACartSlot->LoadROM(romdata, romlen))
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return false;
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if (savedata && savelen)
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GBACart::LoadSave(savedata, savelen);
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GBACartSlot->LoadSave(savedata, savelen);
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return true;
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}
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void LoadGBAAddon(int type)
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{
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GBACart::LoadAddon(type);
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if (GBACartSlot)
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GBACartSlot->LoadAddon(type);
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}
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void EjectGBACart()
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{
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GBACart::EjectCart();
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if (GBACartSlot)
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GBACartSlot->EjectCart();
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}
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void LoadBIOS()
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@ -1493,7 +1499,8 @@ void SetGBASlotTimings()
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// for example, the Cartridge Construction Kit relies on this to determine that
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// the GBA slot is empty
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GBACart::SetOpenBusDecay(openbus[(curcnt>>2) & 0x3]);
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assert(GBACartSlot != nullptr);
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GBACartSlot->SetOpenBusDecay(openbus[(curcnt>>2) & 0x3]);
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}
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@ -2161,12 +2168,14 @@ u8 ARM9Read8(u32 addr)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00; // deselected CPU is 00h-filled
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if (addr & 0x1) return GBACart::ROMRead(addr-1) >> 8;
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return GBACart::ROMRead(addr) & 0xFF;
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assert(GBACartSlot != nullptr);
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if (addr & 0x1) return GBACartSlot->ROMRead(addr-1) >> 8;
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return GBACartSlot->ROMRead(addr) & 0xFF;
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00; // deselected CPU is 00h-filled
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return GBACart::SRAMRead(addr);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->SRAMRead(addr);
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}
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Log(LogLevel::Debug, "unknown arm9 read8 %08X\n", addr);
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@ -2221,12 +2230,14 @@ u16 ARM9Read16(u32 addr)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return 0x0000; // deselected CPU is 00h-filled
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return GBACart::ROMRead(addr);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->ROMRead(addr);
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return 0x0000; // deselected CPU is 00h-filled
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->SRAMRead(addr) |
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(GBACartSlot->SRAMRead(addr+1) << 8);
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}
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//if (addr) Log(LogLevel::Warn, "unknown arm9 read16 %08X %08X\n", addr, ARM9->R[15]);
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@ -2281,15 +2292,17 @@ u32 ARM9Read32(u32 addr)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00000000; // deselected CPU is 00h-filled
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return GBACart::ROMRead(addr) |
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(GBACart::ROMRead(addr+2) << 16);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->ROMRead(addr) |
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(GBACartSlot->ROMRead(addr+2) << 16);
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return 0x00000000; // deselected CPU is 00h-filled
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8) |
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(GBACart::SRAMRead(addr+2) << 16) |
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(GBACart::SRAMRead(addr+3) << 24);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->SRAMRead(addr) |
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(GBACartSlot->SRAMRead(addr+1) << 8) |
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(GBACartSlot->SRAMRead(addr+2) << 16) |
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(GBACartSlot->SRAMRead(addr+3) << 24);
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}
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//Log(LogLevel::Warn, "unknown arm9 read32 %08X | %08X %08X\n", addr, ARM9->R[15], ARM9->R[12]);
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@ -2332,7 +2345,8 @@ void ARM9Write8(u32 addr, u8 val)
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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GBACart::SRAMWrite(addr, val);
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assert(GBACartSlot != nullptr);
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GBACartSlot->SRAMWrite(addr, val);
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return;
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}
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@ -2392,13 +2406,15 @@ void ARM9Write16(u32 addr, u16 val)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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GBACart::ROMWrite(addr, val);
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assert(GBACartSlot != nullptr);
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GBACartSlot->ROMWrite(addr, val);
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return;
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, val >> 8);
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assert(GBACartSlot != nullptr);
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GBACartSlot->SRAMWrite(addr, val & 0xFF);
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GBACartSlot->SRAMWrite(addr+1, val >> 8);
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return;
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}
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@ -2458,16 +2474,18 @@ void ARM9Write32(u32 addr, u32 val)
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case 0x08000000:
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case 0x09000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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GBACart::ROMWrite(addr, val & 0xFFFF);
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GBACart::ROMWrite(addr+2, val >> 16);
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assert(GBACartSlot != nullptr);
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GBACartSlot->ROMWrite(addr, val & 0xFFFF);
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GBACartSlot->ROMWrite(addr+2, val >> 16);
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return;
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case 0x0A000000:
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if (ExMemCnt[0] & (1<<7)) return; // deselected CPU, skip the write
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, (val >> 8) & 0xFF);
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GBACart::SRAMWrite(addr+2, (val >> 16) & 0xFF);
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GBACart::SRAMWrite(addr+3, val >> 24);
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assert(GBACartSlot != nullptr);
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GBACartSlot->SRAMWrite(addr, val & 0xFF);
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GBACartSlot->SRAMWrite(addr+1, (val >> 8) & 0xFF);
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GBACartSlot->SRAMWrite(addr+2, (val >> 16) & 0xFF);
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GBACartSlot->SRAMWrite(addr+3, val >> 24);
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return;
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}
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@ -2559,13 +2577,15 @@ u8 ARM7Read8(u32 addr)
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00; // deselected CPU is 00h-filled
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if (addr & 0x1) return GBACart::ROMRead(addr-1) >> 8;
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return GBACart::ROMRead(addr) & 0xFF;
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assert(GBACartSlot != nullptr);
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if (addr & 0x1) return GBACartSlot->ROMRead(addr-1) >> 8;
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return GBACartSlot->ROMRead(addr) & 0xFF;
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00; // deselected CPU is 00h-filled
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return GBACart::SRAMRead(addr);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->SRAMRead(addr);
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}
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Log(LogLevel::Debug, "unknown arm7 read8 %08X %08X %08X/%08X\n", addr, ARM7->R[15], ARM7->R[0], ARM7->R[1]);
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@ -2625,13 +2645,15 @@ u16 ARM7Read16(u32 addr)
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x0000; // deselected CPU is 00h-filled
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return GBACart::ROMRead(addr);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->ROMRead(addr);
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x0000; // deselected CPU is 00h-filled
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->SRAMRead(addr) |
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(GBACartSlot->SRAMRead(addr+1) << 8);
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}
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Log(LogLevel::Debug, "unknown arm7 read16 %08X %08X\n", addr, ARM7->R[15]);
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@ -2691,16 +2713,18 @@ u32 ARM7Read32(u32 addr)
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00000000; // deselected CPU is 00h-filled
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return GBACart::ROMRead(addr) |
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(GBACart::ROMRead(addr+2) << 16);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->ROMRead(addr) |
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(GBACartSlot->ROMRead(addr+2) << 16);
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return 0x00000000; // deselected CPU is 00h-filled
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return GBACart::SRAMRead(addr) |
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(GBACart::SRAMRead(addr+1) << 8) |
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(GBACart::SRAMRead(addr+2) << 16) |
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(GBACart::SRAMRead(addr+3) << 24);
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assert(GBACartSlot != nullptr);
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return GBACartSlot->SRAMRead(addr) |
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(GBACartSlot->SRAMRead(addr+1) << 8) |
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(GBACartSlot->SRAMRead(addr+2) << 16) |
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(GBACartSlot->SRAMRead(addr+3) << 24);
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}
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//Log(LogLevel::Warn, "unknown arm7 read32 %08X | %08X\n", addr, ARM7->R[15]);
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@ -2765,7 +2789,8 @@ void ARM7Write8(u32 addr, u8 val)
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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GBACart::SRAMWrite(addr, val);
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assert(GBACartSlot != nullptr);
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GBACartSlot->SRAMWrite(addr, val);
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return;
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}
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@ -2839,14 +2864,15 @@ void ARM7Write16(u32 addr, u16 val)
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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GBACart::ROMWrite(addr, val);
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assert(GBACartSlot != nullptr);
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GBACartSlot->ROMWrite(addr, val);
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return;
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, val >> 8);
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GBACartSlot->SRAMWrite(addr, val & 0xFF);
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GBACartSlot->SRAMWrite(addr+1, val >> 8);
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return;
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}
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@ -2920,17 +2946,19 @@ void ARM7Write32(u32 addr, u32 val)
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case 0x09000000:
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case 0x09800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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GBACart::ROMWrite(addr, val & 0xFFFF);
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GBACart::ROMWrite(addr+2, val >> 16);
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assert(GBACartSlot != nullptr);
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GBACartSlot->ROMWrite(addr, val & 0xFFFF);
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GBACartSlot->ROMWrite(addr+2, val >> 16);
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return;
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case 0x0A000000:
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case 0x0A800000:
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if (!(ExMemCnt[0] & (1<<7))) return; // deselected CPU, skip the write
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GBACart::SRAMWrite(addr, val & 0xFF);
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GBACart::SRAMWrite(addr+1, (val >> 8) & 0xFF);
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GBACart::SRAMWrite(addr+2, (val >> 16) & 0xFF);
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GBACart::SRAMWrite(addr+3, val >> 24);
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assert(GBACartSlot != nullptr);
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GBACartSlot->SRAMWrite(addr, val & 0xFF);
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GBACartSlot->SRAMWrite(addr+1, (val >> 8) & 0xFF);
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GBACartSlot->SRAMWrite(addr+2, (val >> 16) & 0xFF);
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GBACartSlot->SRAMWrite(addr+3, val >> 24);
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return;
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}
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