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Slight polish to DMA (#1856)
* Slight polish to DMA - Default-initialize members explicitly - Mark some methods as const noexcept - Initialize DMA::MRAMBurstTable to DMATiming::MRAMDummy - Use the default destructor * Move DMA_Timings definitions to a source file - To ensure constant and unique addresses * Include some extra DMA members in the savestate * Simplify serializing the DMA table - Extend the dummy table to 256 bytes (same length as the real ones) * Revert the type change to DMA::DoSavestate * Keep the MRAMBurstTable inside the DMA class, instead of using a pointer - If we use a pointer to an external table, then we can't use it in savestates (else that external table gets overwritten)
This commit is contained in:
Jesse Talavera-Greenberg
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src/DMA_Timings.cpp
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243
src/DMA_Timings.cpp
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/*
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Copyright 2016-2023 melonDS team
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include "DMA_Timings.h"
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#include "types.h"
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namespace DMATiming
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{
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// DMA timing tables
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//
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// DMA timings on the DS are normally straightforward, except in one case: when
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// main RAM is involved.
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// Main RAM to main RAM is the easy case: 16c/unit in 16bit mode, 18c/unit in 32bit
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// mode.
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// It gets more complicated when transferring from main RAM to somewhere else, or
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// vice versa: main RAM supports burst accesses, but the rules dictating how long
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// bursts can be are weird and inconsistent. Main RAM also supports parallel
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// memory operations, to some extent.
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// I haven't figured out the full logic behind it, let alone how to emulate it
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// efficiently, so for now we will use these tables.
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// A zero denotes the end of a burst pattern.
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//
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// Note: burst patterns only apply when the main RAM address is incrementing.
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// A fixed or decrementing address results in nonsequential accesses.
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//
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// Note about GBA slot/wifi timings: these take into account the sequential timing
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// setting. Timings are such that the nonseq setting only matters for the first
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// access, and minor edge cases (like the last of a 0x20000-byte block).
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extern const std::array<u8, 256> MRAMDummy = {0};
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extern const std::array<u8, 256> MRAMRead16Bursts[] =
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{
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// main RAM to regular 16bit or 32bit bus (similar)
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{7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2,
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7, 3, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2,
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7, 3,
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0},
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// main RAM to GBA/wifi, seq=4
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{8, 6, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5,
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0},
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// main RAM to GBA/wifi, seq=6
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{10, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7,
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12, 8,
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0},
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};
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extern const std::array<u8, 256> MRAMRead32Bursts[] =
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{
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// main RAM to regular 16bit bus
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{9, 4, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 9,
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0},
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// main RAM to regular 32bit bus
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{9, 3, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2,
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0},
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// main RAM to GBA/wifi, seq=4
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{14, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13, 10, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9, 9, 9, 9,
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9, 9, 9, 9, 9, 9, 9,
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13,
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0},
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// main RAM to GBA/wifi, seq=6
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{18, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17, 14, 13, 13, 13, 13, 13, 13, 13, 13,
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13, 13, 13, 13, 13, 13, 13, 13, 13,
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17,
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0},
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};
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extern const std::array<u8, 256> MRAMWrite16Bursts[] =
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{
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// regular 16bit or 32bit bus to main RAM (similar)
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{8, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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0},
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// GBA/wifi to main RAM, seq=4
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{10, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
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5, 5, 5, 5, 5, 5, 5, 5,
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0},
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// GBA/wifi to main RAM, seq=6
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{9, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
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7, 7, 7, 7, 7,
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0},
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};
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extern const std::array<u8, 256> MRAMWrite32Bursts[4] =
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{
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// regular 16bit bus to main RAM
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{9, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
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0},
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// regular 32bit bus to main RAM
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{9, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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0},
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// GBA/wifi to main RAM, seq=4
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{15, 10, 10, 10, 10, 10, 10, 10, 10, 10,
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10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
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10, 10, 10, 10,
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0},
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// GBA/wifi to main RAM, seq=6
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{16, 14, 14, 14, 14, 14, 14, 14, 14, 14,
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14, 14, 14, 14, 14, 14, 14, 14,
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0},
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};
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}
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