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add PoC ARM9 instruction cache logic. not actually in use, but it's there as a reference (and if we ever need it).

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This commit is contained in:
StapleButter
2019-01-04 21:47:06 +01:00
parent 1e35d18ce6
commit 90f2c0834e
3 changed files with 172 additions and 24 deletions
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15
src/ARM.h
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@ -173,7 +173,7 @@ public:
s32 Execute();
// all code accesses are forced nonseq 32bit
u32 CodeRead32(u32 addr);
u32 CodeRead32(u32 addr, bool branch);
void DataRead8(u32 addr, u32* val);
void DataRead16(u32 addr, u32* val);
@ -233,11 +233,19 @@ public:
void UpdatePURegions();
u32 RandomLineIndex();
void ICacheLookup(u32 addr);
void ICacheInvalidateByAddr(u32 addr);
void ICacheInvalidateAll();
void CP15Write(u32 id, u32 val);
u32 CP15Read(u32 id);
u32 CP15Control;
u32 RNGSeed;
u32 DTCMSetting, ITCMSetting;
u8 ITCM[0x8000];
@ -245,6 +253,10 @@ public:
u8 DTCM[0x4000];
u32 DTCMBase, DTCMSize;
u8 ICache[0x2000];
u32 ICacheTags[64*4];
u8 ICacheCount[64];
u32 PU_CodeCacheable;
u32 PU_DataCacheable;
u32 PU_DataCacheWrite;
@ -265,6 +277,7 @@ public:
u8 MemTimings[0x100000][4];
s32 RegionCodeCycles;
u8* CurICacheLine;
};
class ARMv4 : public ARM