mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
add PoC ARM9 instruction cache logic. not actually in use, but it's there as a reference (and if we ever need it).
This commit is contained in:
145
src/CP15.cpp
145
src/CP15.cpp
@ -35,6 +35,8 @@ void ARMv5::CP15Reset()
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{
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CP15Control = 0x2078; // dunno
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RNGSeed = 44203;
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DTCMSetting = 0;
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ITCMSetting = 0;
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@ -45,6 +47,10 @@ void ARMv5::CP15Reset()
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DTCMBase = 0xFFFFFFFF;
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DTCMSize = 0;
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memset(ICache, 0, 0x2000);
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ICacheInvalidateAll();
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memset(ICacheCount, 0, 64);
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PU_CodeCacheable = 0;
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PU_DataCacheable = 0;
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PU_DataCacheWrite = 0;
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@ -54,6 +60,8 @@ void ARMv5::CP15Reset()
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memset(PU_Region, 0, 8*sizeof(u32));
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UpdatePURegions();
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CurICacheLine = NULL;
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}
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void ARMv5::CP15DoSavestate(Savestate* file)
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@ -276,6 +284,119 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
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}
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u32 ARMv5::RandomLineIndex()
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{
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// lame RNG, but good enough for this purpose
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u32 s = RNGSeed;
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RNGSeed ^= (s*17);
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RNGSeed ^= (s*7);
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return (RNGSeed >> 17) & 0x3;
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}
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int zog=1;
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void ARMv5::ICacheLookup(u32 addr)
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{
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u32 tag = addr & 0xFFFFF800;
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u32 id = (addr >> 5) & 0x3F;
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id <<= 2;
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if (ICacheTags[id+0] == tag)
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{
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CodeCycles = 1;zog=1;
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CurICacheLine = &ICache[(id+0) << 5];
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return;
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}
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if (ICacheTags[id+1] == tag)
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{
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CodeCycles = 1;zog=2;
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CurICacheLine = &ICache[(id+1) << 5];
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return;
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}
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if (ICacheTags[id+2] == tag)
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{
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CodeCycles = 1;zog=3;
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CurICacheLine = &ICache[(id+2) << 5];
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return;
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}
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if (ICacheTags[id+3] == tag)
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{
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CodeCycles = 1;zog=4;
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CurICacheLine = &ICache[(id+3) << 5];
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return;
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}
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// cache miss
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u32 line;
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if (CP15Control & (1<<14))
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{
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line = ICacheCount[id>>2];
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ICacheCount[id>>2] = (line+1) & 0x3;
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}
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else
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{
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line = RandomLineIndex();
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}
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line += id;
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addr &= ~0x1F;
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u8* ptr = &ICache[line << 5];
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if (CodeMem.Mem)
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{
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memcpy(ptr, &CodeMem.Mem[addr & CodeMem.Mask], 32);
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}
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else
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{
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for (int i = 0; i < 32; i+=4)
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*(u32*)&ptr[i] = NDS::ARM9Read32(addr+i);
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}
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ICacheTags[line] = tag;
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// ouch :/
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//printf("cache miss %08X: %d/%d\n", addr, NDS::ARM9MemTimings[addr >> 14][2], NDS::ARM9MemTimings[addr >> 14][3]);
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CodeCycles = (NDS::ARM9MemTimings[addr >> 14][2] + (NDS::ARM9MemTimings[addr >> 14][3] * 7)) << ClockShift;
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CurICacheLine = ptr;
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}
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void ARMv5::ICacheInvalidateByAddr(u32 addr)
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{
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u32 tag = addr & 0xFFFFF800;
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u32 id = (addr >> 5) & 0x3F;
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id <<= 2;
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if (ICacheTags[id+0] == tag)
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{
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ICacheTags[id+0] = 1;
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return;
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}
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if (ICacheTags[id+1] == tag)
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{
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ICacheTags[id+1] = 1;
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return;
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}
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if (ICacheTags[id+2] == tag)
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{
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ICacheTags[id+2] = 1;
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return;
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}
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if (ICacheTags[id+3] == tag)
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{
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ICacheTags[id+3] = 1;
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return;
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}
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}
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void ARMv5::ICacheInvalidateAll()
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{
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for (int i = 0; i < 64*4; i++)
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ICacheTags[i] = 1;
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}
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void ARMv5::CP15Write(u32 id, u32 val)
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{
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//printf("CP15 write op %03X %08X %08X\n", id, val, NDS::ARM9->R[15]);
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@ -391,6 +512,17 @@ void ARMv5::CP15Write(u32 id, u32 val)
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return;
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case 0x750:
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ICacheInvalidateAll();
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return;
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case 0x751:
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ICacheInvalidateByAddr(val);
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return;
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case 0x752:
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printf("CP15: ICACHE INVALIDATE WEIRD. %08X\n", val);
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return;
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case 0x761:
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//printf("inval data cache %08X\n", val);
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return;
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@ -519,7 +651,7 @@ u32 ARMv5::CP15Read(u32 id)
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// TCM are handled here.
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// TODO: later on, handle PU, and maybe caches
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u32 ARMv5::CodeRead32(u32 addr)
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u32 ARMv5::CodeRead32(u32 addr, bool branch)
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{
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if (addr < ITCMSize)
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{
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@ -528,11 +660,14 @@ u32 ARMv5::CodeRead32(u32 addr)
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}
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CodeCycles = RegionCodeCycles;
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if (CodeCycles == 0xFF)
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if (CodeCycles == 0xFF) // cached memory. hax
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{
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// sort of code cache hit/miss average
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if (!(addr & 0x1F)) CodeCycles = kCodeCacheTiming;
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else CodeCycles = 1;
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if (branch || !(addr & 0x1F))
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CodeCycles = kCodeCacheTiming;//ICacheLookup(addr);
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else
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CodeCycles = 1;
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//return *(u32*)&CurICacheLine[addr & 0x1C];
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}
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if (CodeMem.Mem) return *(u32*)&CodeMem.Mem[addr & CodeMem.Mask];
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