mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-06-28 01:49:42 -06:00
fix copyright headers
This commit is contained in:
@ -1,5 +1,5 @@
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/*
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/*
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Copyright 2016-2022 melonDS team, RSDuck
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Copyright 2016-2022 melonDS team
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This file is part of melonDS.
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This file is part of melonDS.
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@ -1,5 +1,5 @@
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/*
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/*
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Copyright 2016-2022 melonDS team, RSDuck
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Copyright 2016-2022 melonDS team
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||||||
|
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This file is part of melonDS.
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This file is part of melonDS.
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@ -1,5 +1,5 @@
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/*
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/*
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Copyright 2016-2022 melonDS team, RSDuck
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Copyright 2016-2022 melonDS team
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|
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This file is part of melonDS.
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This file is part of melonDS.
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@ -55,7 +55,7 @@
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and map the memory regions as they're structured on the DS
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and map the memory regions as they're structured on the DS
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in it.
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in it.
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On most systems you have a single piece of main ram,
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On most systems you have a single piece of main ram,
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maybe some video ram and faster cache RAM and that's about it.
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maybe some video ram and faster cache RAM and that's about it.
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Here we have not only a lot more different memory regions,
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Here we have not only a lot more different memory regions,
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but also two address spaces. Not only that but they all have
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but also two address spaces. Not only that but they all have
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@ -119,7 +119,7 @@ void HandleFault(u64 pc, u64 lr, u64 fp, u64 faultAddr, u32 desc);
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extern "C"
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extern "C"
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{
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{
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void ARM_RestoreContext(u64* registers) __attribute__((noreturn));
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void ARM_RestoreContext(u64* registers) __attribute__((noreturn));
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extern char __start__;
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extern char __start__;
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@ -146,7 +146,7 @@ void __libnx_exception_handler(ThreadExceptionDump* ctx)
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{
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{
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integerRegisters[32] = (u64)desc.FaultPC;
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integerRegisters[32] = (u64)desc.FaultPC;
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ARM_RestoreContext(integerRegisters);
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ARM_RestoreContext(integerRegisters);
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}
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}
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HandleFault(ctx->pc.x, ctx->lr.x, ctx->fp.x, ctx->far.x, ctx->error_desc);
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HandleFault(ctx->pc.x, ctx->lr.x, ctx->fp.x, ctx->far.x, ctx->error_desc);
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@ -311,7 +311,7 @@ bool MapIntoRange(u32 addr, u32 num, u32 offset, u32 size)
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{
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{
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u8* dst = (u8*)(num == 0 ? FastMem9Start : FastMem7Start) + addr;
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u8* dst = (u8*)(num == 0 ? FastMem9Start : FastMem7Start) + addr;
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#ifdef __SWITCH__
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#ifdef __SWITCH__
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Result r = (svcMapProcessMemory(dst, envGetOwnProcessHandle(),
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Result r = (svcMapProcessMemory(dst, envGetOwnProcessHandle(),
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(u64)(MemoryBaseCodeMem + offset), size));
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(u64)(MemoryBaseCodeMem + offset), size));
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return R_SUCCEEDED(r);
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return R_SUCCEEDED(r);
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#elif defined(_WIN32)
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#elif defined(_WIN32)
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@ -452,7 +452,7 @@ void SetCodeProtection(int region, u32 offset, bool protect)
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u32 effectiveAddr = mapping.Addr + (offset - mapping.LocalOffset);
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u32 effectiveAddr = mapping.Addr + (offset - mapping.LocalOffset);
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if (mapping.Num == 0
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if (mapping.Num == 0
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&& region != memregion_DTCM
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&& region != memregion_DTCM
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&& (effectiveAddr & NDS::ARM9->DTCMMask) == NDS::ARM9->DTCMBase)
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&& (effectiveAddr & NDS::ARM9->DTCMMask) == NDS::ARM9->DTCMBase)
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continue;
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continue;
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@ -621,7 +621,7 @@ bool MapAtAddress(u32 addr)
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// this overcomplicated piece of code basically just finds whole pieces of code memory
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// this overcomplicated piece of code basically just finds whole pieces of code memory
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// which can be mapped/protected
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// which can be mapped/protected
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u32 offset = 0;
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u32 offset = 0;
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bool skipDTCM = num == 0 && region != memregion_DTCM;
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bool skipDTCM = num == 0 && region != memregion_DTCM;
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while (offset < mirrorSize)
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while (offset < mirrorSize)
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{
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{
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@ -700,10 +700,10 @@ void Init()
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virtmemLock();
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virtmemLock();
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MemoryBaseCodeMem = (u8*)virtmemFindCodeMemory(MemoryTotalSize, 0x1000);
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MemoryBaseCodeMem = (u8*)virtmemFindCodeMemory(MemoryTotalSize, 0x1000);
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bool succeded = R_SUCCEEDED(svcMapProcessCodeMemory(envGetOwnProcessHandle(), (u64)MemoryBaseCodeMem,
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bool succeded = R_SUCCEEDED(svcMapProcessCodeMemory(envGetOwnProcessHandle(), (u64)MemoryBaseCodeMem,
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(u64)MemoryBase, MemoryTotalSize));
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(u64)MemoryBase, MemoryTotalSize));
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assert(succeded);
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assert(succeded);
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succeded = R_SUCCEEDED(svcSetProcessMemoryPermission(envGetOwnProcessHandle(), (u64)MemoryBaseCodeMem,
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succeded = R_SUCCEEDED(svcSetProcessMemoryPermission(envGetOwnProcessHandle(), (u64)MemoryBaseCodeMem,
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MemoryTotalSize, Perm_Rw));
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MemoryTotalSize, Perm_Rw));
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assert(succeded);
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assert(succeded);
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@ -740,7 +740,7 @@ void Init()
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u8* basePtr = MemoryBase;
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u8* basePtr = MemoryBase;
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#else
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#else
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// this used to be allocated with three different mmaps
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// this used to be allocated with three different mmaps
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// The idea was to give the OS more freedom where to position the buffers,
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// The idea was to give the OS more freedom where to position the buffers,
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// but something was bad about this so instead we take this vmem eating monster
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// but something was bad about this so instead we take this vmem eating monster
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// which seems to work better.
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// which seems to work better.
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MemoryBase = (u8*)mmap(NULL, AddrSpaceSize*4, PROT_NONE, MAP_ANON | MAP_PRIVATE, -1, 0);
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MemoryBase = (u8*)mmap(NULL, AddrSpaceSize*4, PROT_NONE, MAP_ANON | MAP_PRIVATE, -1, 0);
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@ -855,7 +855,7 @@ bool IsFastmemCompatible(int region)
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TODO: with some hacks, the smaller shared WRAM regions
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TODO: with some hacks, the smaller shared WRAM regions
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could be mapped in some occaisons as well
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could be mapped in some occaisons as well
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*/
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*/
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if (region == memregion_DTCM
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if (region == memregion_DTCM
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|| region == memregion_SharedWRAM
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|| region == memregion_SharedWRAM
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|| region == memregion_NewSharedWRAM_B
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|| region == memregion_NewSharedWRAM_B
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|| region == memregion_NewSharedWRAM_C)
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|| region == memregion_NewSharedWRAM_C)
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@ -1071,7 +1071,7 @@ int ClassifyAddress9(u32 addr)
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{
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{
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return memregion_DTCM;
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return memregion_DTCM;
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}
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}
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else
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else
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{
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{
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if (NDS::ConsoleType == 1 && addr >= 0xFFFF0000 && !(DSi::SCFG_BIOS & (1<<1)))
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if (NDS::ConsoleType == 1 && addr >= 0xFFFF0000 && !(DSi::SCFG_BIOS & (1<<1)))
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{
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{
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@ -1219,8 +1219,8 @@ void* GetFuncForAddr(ARM* cpu, u32 addr, bool store, int size)
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{
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{
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switch (size | store)
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switch (size | store)
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{
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{
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case 8: return (void*)GPU3D::Read8;
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case 8: return (void*)GPU3D::Read8;
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case 9: return (void*)GPU3D::Write8;
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case 9: return (void*)GPU3D::Write8;
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case 16: return (void*)GPU3D::Read16;
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case 16: return (void*)GPU3D::Read16;
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case 17: return (void*)GPU3D::Write16;
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case 17: return (void*)GPU3D::Write16;
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case 32: return (void*)GPU3D::Read32;
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case 32: return (void*)GPU3D::Read32;
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@ -1256,7 +1256,7 @@ void* GetFuncForAddr(ARM* cpu, u32 addr, bool store, int size)
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case 0x06000000:
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case 0x06000000:
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switch (size | store)
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switch (size | store)
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{
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{
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case 8: return (void*)VRAMRead<u8>;
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case 8: return (void*)VRAMRead<u8>;
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case 9: return NULL;
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case 9: return NULL;
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case 16: return (void*)VRAMRead<u16>;
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case 16: return (void*)VRAMRead<u16>;
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case 17: return (void*)VRAMWrite<u16>;
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case 17: return (void*)VRAMWrite<u16>;
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@ -1275,8 +1275,8 @@ void* GetFuncForAddr(ARM* cpu, u32 addr, bool store, int size)
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{
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{
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switch (size | store)
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switch (size | store)
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{
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{
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case 8: return (void*)SPU::Read8;
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case 8: return (void*)SPU::Read8;
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case 9: return (void*)SPU::Write8;
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case 9: return (void*)SPU::Write8;
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case 16: return (void*)SPU::Read16;
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case 16: return (void*)SPU::Read16;
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case 17: return (void*)SPU::Write16;
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case 17: return (void*)SPU::Write16;
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case 32: return (void*)SPU::Read32;
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case 32: return (void*)SPU::Read32;
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@ -1289,7 +1289,7 @@ void* GetFuncForAddr(ARM* cpu, u32 addr, bool store, int size)
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switch (size | store)
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switch (size | store)
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{
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{
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case 8: return (void*)NDS::ARM7IORead8;
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case 8: return (void*)NDS::ARM7IORead8;
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case 9: return (void*)NDS::ARM7IOWrite8;
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case 9: return (void*)NDS::ARM7IOWrite8;
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case 16: return (void*)NDS::ARM7IORead16;
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case 16: return (void*)NDS::ARM7IORead16;
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case 17: return (void*)NDS::ARM7IOWrite16;
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case 17: return (void*)NDS::ARM7IOWrite16;
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case 32: return (void*)NDS::ARM7IORead32;
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case 32: return (void*)NDS::ARM7IORead32;
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@ -1301,7 +1301,7 @@ void* GetFuncForAddr(ARM* cpu, u32 addr, bool store, int size)
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switch (size | store)
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switch (size | store)
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{
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{
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case 8: return (void*)DSi::ARM7IORead8;
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case 8: return (void*)DSi::ARM7IORead8;
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case 9: return (void*)DSi::ARM7IOWrite8;
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case 9: return (void*)DSi::ARM7IOWrite8;
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case 16: return (void*)DSi::ARM7IORead16;
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case 16: return (void*)DSi::ARM7IORead16;
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case 17: return (void*)DSi::ARM7IOWrite16;
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case 17: return (void*)DSi::ARM7IOWrite16;
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case 32: return (void*)DSi::ARM7IORead32;
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case 32: return (void*)DSi::ARM7IORead32;
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@ -1,5 +1,5 @@
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/*
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/*
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Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
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||||||
|
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This file is part of melonDS.
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This file is part of melonDS.
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|
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@ -78,4 +78,4 @@ void* GetFuncForAddr(ARM* cpu, u32 addr, bool store, int size);
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|
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}
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}
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#endif
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#endif
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@ -1,5 +1,5 @@
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/*
|
/*
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||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
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||||||
|
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This file is part of melonDS.
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This file is part of melonDS.
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|
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@ -364,7 +364,7 @@ void Compiler::A_Comp_Mul_Long()
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{
|
{
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BSR(32, RSCRATCH, R(RSCRATCH3));
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BSR(32, RSCRATCH, R(RSCRATCH3));
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}
|
}
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|
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SHR(32, R(RSCRATCH), Imm8(3));
|
SHR(32, R(RSCRATCH), Imm8(3));
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SetJumpTarget(zeroBSR); // fortunately that's even right
|
SetJumpTarget(zeroBSR); // fortunately that's even right
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Comp_AddCycles_CI(RSCRATCH, 2);
|
Comp_AddCycles_CI(RSCRATCH, 2);
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@ -617,7 +617,7 @@ void Compiler::T_Comp_AddSub_()
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int op = (CurInstr.Instr >> 9) & 0x3;
|
int op = (CurInstr.Instr >> 9) & 0x3;
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|
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OpArg rn = op >= 2 ? Imm32((CurInstr.Instr >> 6) & 0x7) : MapReg(CurInstr.T_Reg(6));
|
OpArg rn = op >= 2 ? Imm32((CurInstr.Instr >> 6) & 0x7) : MapReg(CurInstr.T_Reg(6));
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|
|
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Comp_AddCycles_C();
|
Comp_AddCycles_C();
|
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|
|
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// special case for thumb mov being alias to add rd, rn, #0
|
// special case for thumb mov being alias to add rd, rn, #0
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|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
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@ -30,7 +30,7 @@ int squeezePointer(T* ptr)
|
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assert((T*)((u64)truncated) == ptr);
|
assert((T*)((u64)truncated) == ptr);
|
||||||
return truncated;
|
return truncated;
|
||||||
}
|
}
|
||||||
|
|
||||||
void Compiler::Comp_JumpTo(u32 addr, bool forceNonConstantCycles)
|
void Compiler::Comp_JumpTo(u32 addr, bool forceNonConstantCycles)
|
||||||
{
|
{
|
||||||
// we can simplify constant branches by a lot
|
// we can simplify constant branches by a lot
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
@ -121,7 +121,7 @@ public:
|
|||||||
void A_Comp_Mul_Long();
|
void A_Comp_Mul_Long();
|
||||||
|
|
||||||
void A_Comp_CLZ();
|
void A_Comp_CLZ();
|
||||||
|
|
||||||
void A_Comp_MemWB();
|
void A_Comp_MemWB();
|
||||||
void A_Comp_MemHalf();
|
void A_Comp_MemHalf();
|
||||||
void A_Comp_LDM_STM();
|
void A_Comp_LDM_STM();
|
||||||
@ -170,7 +170,7 @@ public:
|
|||||||
s32 Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode, bool skipLoadingRn);
|
s32 Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode, bool skipLoadingRn);
|
||||||
bool Comp_MemLoadLiteral(int size, bool signExtend, int rd, u32 addr);
|
bool Comp_MemLoadLiteral(int size, bool signExtend, int rd, u32 addr);
|
||||||
|
|
||||||
void Comp_ArithTriOp(void (Compiler::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
|
void Comp_ArithTriOp(void (Compiler::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
|
||||||
Gen::OpArg rd, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed, int opFlags);
|
Gen::OpArg rd, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed, int opFlags);
|
||||||
void Comp_ArithTriOpReverse(void (Compiler::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
|
void Comp_ArithTriOpReverse(void (Compiler::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
|
||||||
Gen::OpArg rd, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed, int opFlags);
|
Gen::OpArg rd, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed, int opFlags);
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, RSDuck
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
@ -222,7 +222,7 @@ enum
|
|||||||
tk_POP,
|
tk_POP,
|
||||||
tk_LDMIA,
|
tk_LDMIA,
|
||||||
tk_STMIA,
|
tk_STMIA,
|
||||||
|
|
||||||
tk_BCOND,
|
tk_BCOND,
|
||||||
tk_BX,
|
tk_BX,
|
||||||
tk_BLX_REG,
|
tk_BLX_REG,
|
||||||
@ -278,4 +278,4 @@ Info Decode(bool thumb, u32 num, u32 instr);
|
|||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, Raphaël Zumer
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, Raphaël Zumer
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, WaluigiWare64
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, WaluigiWare64
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2020 Arisotura
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2020 Arisotura
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, WaluigiWare64
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, WaluigiWare64
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2021 Rayyan Ansari
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2021 Rayyan Ansari
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
melonDS is free software: you can redistribute it and/or modify it under
|
melonDS is free software: you can redistribute it and/or modify it under
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, WaluigiWare64
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
@ -1,5 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
Copyright 2016-2022 melonDS team, WaluigiWare64
|
Copyright 2016-2022 melonDS team
|
||||||
|
|
||||||
This file is part of melonDS.
|
This file is part of melonDS.
|
||||||
|
|
||||||
|
Reference in New Issue
Block a user