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https://github.com/melonDS-emu/melonDS.git
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move ARM64 JIT backend here
This commit is contained in:
RSDuck
707
src/ARMJIT_A64/ARMJIT_Compiler.cpp
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707
src/ARMJIT_A64/ARMJIT_Compiler.cpp
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@ -0,0 +1,707 @@
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#include "ARMJIT_Compiler.h"
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#include "../ARMInterpreter.h"
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#include "../ARMJIT_Internal.h"
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#ifdef __SWITCH__
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#include "../switch/compat_switch.h"
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extern char __start__;
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#endif
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#include <malloc.h>
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using namespace Arm64Gen;
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namespace ARMJIT
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{
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/*
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Recompiling classic ARM to ARMv8 code is at the same time
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easier and trickier than compiling to a less related architecture
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like x64. At one hand you can translate a lot of instructions directly.
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But at the same time, there are a ton of exceptions, like for
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example ADD and SUB can't have a RORed second operand on ARMv8.
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*/
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template <>
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const ARM64Reg RegisterCache<Compiler, ARM64Reg>::NativeRegAllocOrder[] =
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{W19, W20, W21, W22, W23, W24, W25, W26};
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template <>
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const int RegisterCache<Compiler, ARM64Reg>::NativeRegsAvailable = 8;
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const int JitMemSize = 16 * 1024 * 1024;
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void Compiler::MovePC()
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{
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ADD(MapReg(15), MapReg(15), Thumb ? 2 : 4);
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}
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Compiler::Compiler()
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{
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#ifdef __SWITCH__
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JitRWBase = memalign(0x1000, JitMemSize);
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JitRXStart = (u8*)&__start__ - JitMemSize - 0x1000;
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JitRWStart = virtmemReserve(JitMemSize);
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MemoryInfo info = {0};
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u32 pageInfo = {0};
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int i = 0;
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while (JitRXStart != NULL)
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{
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svcQueryMemory(&info, &pageInfo, (u64)JitRXStart);
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if (info.type != MemType_Unmapped)
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JitRXStart = (void*)((u8*)info.addr - JitMemSize - 0x1000);
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else
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break;
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if (i++ > 8)
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{
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printf("couldn't find unmapped place for jit memory\n");
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JitRXStart = NULL;
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}
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}
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assert(JitRXStart != NULL);
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bool succeded = R_SUCCEEDED(svcMapProcessCodeMemory(envGetOwnProcessHandle(), (u64)JitRXStart, (u64)JitRWBase, JitMemSize));
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assert(succeded);
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succeded = R_SUCCEEDED(svcSetProcessMemoryPermission(envGetOwnProcessHandle(), (u64)JitRXStart, JitMemSize, Perm_Rx));
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assert(succeded);
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succeded = R_SUCCEEDED(svcMapProcessMemory(JitRWStart, envGetOwnProcessHandle(), (u64)JitRXStart, JitMemSize));
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assert(succeded);
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SetCodeBase((u8*)JitRWStart, (u8*)JitRXStart);
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JitMemUseableSize = JitMemSize;
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Reset();
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#endif
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for (int i = 0; i < 3; i++)
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{
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for (int j = 0; j < 2; j++)
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{
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MemFunc9[i][j] = Gen_MemoryRoutine9(8 << i, j);
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}
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}
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MemFunc7[0][0] = (void*)NDS::ARM7Read8;
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MemFunc7[1][0] = (void*)NDS::ARM7Read16;
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MemFunc7[2][0] = (void*)NDS::ARM7Read32;
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MemFunc7[0][1] = (void*)NDS::ARM7Write8;
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MemFunc7[1][1] = (void*)NDS::ARM7Write16;
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MemFunc7[2][1] = (void*)NDS::ARM7Write32;
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for (int i = 0; i < 2; i++)
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{
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for (int j = 0; j < 2; j++)
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{
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MemFuncsSeq9[i][j] = Gen_MemoryRoutine9Seq(i, j);
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MemFuncsSeq7[i][j] = Gen_MemoryRoutine7Seq(i, j);
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}
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}
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for (int i = 0; i < 3; i++)
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{
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JumpToFuncs9[i] = Gen_JumpTo9(i);
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JumpToFuncs7[i] = Gen_JumpTo7(i);
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}
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/*
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W0 - mode
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W1 - reg num
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W3 - in/out value of reg
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*/
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{
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ReadBanked = GetRXPtr();
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ADD(X2, RCPU, X1, ArithOption(X1, ST_LSL, 2));
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CMP(W0, 0x11);
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FixupBranch fiq = B(CC_EQ);
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SUBS(W1, W1, 13 - 8);
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ADD(X2, RCPU, X1, ArithOption(X1, ST_LSL, 2));
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FixupBranch notEverything = B(CC_LT);
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CMP(W0, 0x12);
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FixupBranch irq = B(CC_EQ);
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CMP(W0, 0x13);
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FixupBranch svc = B(CC_EQ);
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CMP(W0, 0x17);
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FixupBranch abt = B(CC_EQ);
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CMP(W0, 0x1B);
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FixupBranch und = B(CC_EQ);
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SetJumpTarget(notEverything);
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RET();
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SetJumpTarget(fiq);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_FIQ));
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RET();
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SetJumpTarget(irq);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_IRQ));
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RET();
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SetJumpTarget(svc);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_SVC));
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RET();
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SetJumpTarget(abt);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_ABT));
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RET();
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SetJumpTarget(und);
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LDR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_UND));
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RET();
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}
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{
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WriteBanked = GetRXPtr();
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ADD(X2, RCPU, X1, ArithOption(X1, ST_LSL, 2));
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CMP(W0, 0x11);
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FixupBranch fiq = B(CC_EQ);
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SUBS(W1, W1, 13 - 8);
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ADD(X2, RCPU, X1, ArithOption(X1, ST_LSL, 2));
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FixupBranch notEverything = B(CC_LT);
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CMP(W0, 0x12);
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FixupBranch irq = B(CC_EQ);
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CMP(W0, 0x13);
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FixupBranch svc = B(CC_EQ);
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CMP(W0, 0x17);
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FixupBranch abt = B(CC_EQ);
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CMP(W0, 0x1B);
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FixupBranch und = B(CC_EQ);
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SetJumpTarget(notEverything);
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MOVI2R(W4, 0);
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RET();
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SetJumpTarget(fiq);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_FIQ));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(irq);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_IRQ));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(svc);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_SVC));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(abt);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_ABT));
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MOVI2R(W4, 1);
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RET();
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SetJumpTarget(und);
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STR(INDEX_UNSIGNED, W3, X2, offsetof(ARM, R_UND));
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MOVI2R(W4, 1);
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RET();
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}
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//FlushIcache();
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JitMemUseableSize -= GetCodeOffset();
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SetCodeBase((u8*)GetRWPtr(), (u8*)GetRXPtr());
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}
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Compiler::~Compiler()
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{
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#ifdef __SWITCH__
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if (JitRWStart != NULL)
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{
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bool succeded = R_SUCCEEDED(svcUnmapProcessMemory(JitRWStart, envGetOwnProcessHandle(), (u64)JitRXStart, JitMemSize));
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assert(succeded);
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virtmemFree(JitRWStart, JitMemSize);
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succeded = R_SUCCEEDED(svcUnmapProcessCodeMemory(envGetOwnProcessHandle(), (u64)JitRXStart, (u64)JitRWBase, JitMemSize));
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assert(succeded);
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free(JitRWBase);
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}
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#endif
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}
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void Compiler::LoadReg(int reg, ARM64Reg nativeReg)
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{
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if (reg == 15)
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MOVI2R(nativeReg, R15);
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else
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LDR(INDEX_UNSIGNED, nativeReg, RCPU, offsetof(ARM, R[reg]));
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}
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void Compiler::SaveReg(int reg, ARM64Reg nativeReg)
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{
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STR(INDEX_UNSIGNED, nativeReg, RCPU, offsetof(ARM, R[reg]));
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}
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void Compiler::LoadCPSR()
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{
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assert(!CPSRDirty);
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LDR(INDEX_UNSIGNED, RCPSR, RCPU, offsetof(ARM, CPSR));
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}
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void Compiler::SaveCPSR(bool markClean)
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{
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if (CPSRDirty)
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{
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STR(INDEX_UNSIGNED, RCPSR, RCPU, offsetof(ARM, CPSR));
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CPSRDirty = CPSRDirty && !markClean;
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}
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}
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FixupBranch Compiler::CheckCondition(u32 cond)
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{
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if (cond >= 0x8)
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{
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LSR(W1, RCPSR, 28);
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MOVI2R(W2, 1);
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LSLV(W2, W2, W1);
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ANDI2R(W2, W2, ARM::ConditionTable[cond], W3);
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return CBZ(W2);
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}
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else
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{
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u8 bit = (28 + ((~(cond >> 1) & 1) << 1 | (cond >> 2 & 1) ^ (cond >> 1 & 1)));
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if (cond & 1)
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return TBNZ(RCPSR, bit);
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else
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return TBZ(RCPSR, bit);
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}
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}
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#define F(x) &Compiler::A_Comp_##x
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const Compiler::CompileFunc A_Comp[ARMInstrInfo::ak_Count] =
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{
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// AND
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// EOR
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// SUB
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// RSB
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// ADD
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// ADC
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// SBC
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// RSC
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// ORR
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// MOV
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F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
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F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
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// BIC
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
|
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F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp), F(ALUTriOp),
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// MVN
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F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
|
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F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp), F(ALUMovOp),
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// TST
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F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
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// TEQ
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F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
|
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// CMP
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||||
F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
|
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// CMN
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||||
F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp), F(ALUCmpOp),
|
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// Mul
|
||||
F(Mul), F(Mul), F(Mul_Long), F(Mul_Long), F(Mul_Long), F(Mul_Long), NULL, NULL, NULL, NULL, NULL,
|
||||
// ARMv5 exclusives
|
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F(Clz), NULL, NULL, NULL, NULL,
|
||||
|
||||
// STR
|
||||
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
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// STRB
|
||||
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
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// LDR
|
||||
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
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// LDRB
|
||||
F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB), F(MemWB),
|
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// STRH
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F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
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// LDRD
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NULL, NULL, NULL, NULL,
|
||||
// STRD
|
||||
NULL, NULL, NULL, NULL,
|
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// LDRH
|
||||
F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
||||
// LDRSB
|
||||
F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
||||
// LDRSH
|
||||
F(MemHD), F(MemHD), F(MemHD), F(MemHD),
|
||||
// Swap
|
||||
NULL, NULL,
|
||||
// LDM, STM
|
||||
F(LDM_STM), F(LDM_STM),
|
||||
// Branch
|
||||
F(BranchImm), F(BranchImm), F(BranchImm), F(BranchXchangeReg), F(BranchXchangeReg),
|
||||
// Special
|
||||
NULL, NULL, NULL, NULL, NULL, NULL, NULL
|
||||
};
|
||||
#undef F
|
||||
#define F(x) &Compiler::T_Comp_##x
|
||||
const Compiler::CompileFunc T_Comp[ARMInstrInfo::tk_Count] =
|
||||
{
|
||||
// Shift imm
|
||||
F(ShiftImm), F(ShiftImm), F(ShiftImm),
|
||||
// Add/sub tri operand
|
||||
F(AddSub_), F(AddSub_), F(AddSub_), F(AddSub_),
|
||||
// 8 bit imm
|
||||
F(ALUImm8), F(ALUImm8), F(ALUImm8), F(ALUImm8),
|
||||
// ALU
|
||||
F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU),
|
||||
F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU), F(ALU),
|
||||
// ALU hi reg
|
||||
F(ALU_HiReg), F(ALU_HiReg), F(ALU_HiReg),
|
||||
// PC/SP relative ops
|
||||
F(RelAddr), F(RelAddr), F(AddSP),
|
||||
// LDR PC rel
|
||||
F(LoadPCRel),
|
||||
// LDR/STR reg offset
|
||||
F(MemReg), F(MemReg), F(MemReg), F(MemReg),
|
||||
// LDR/STR sign extended, half
|
||||
F(MemRegHalf), F(MemRegHalf), F(MemRegHalf), F(MemRegHalf),
|
||||
// LDR/STR imm offset
|
||||
F(MemImm), F(MemImm), F(MemImm), F(MemImm),
|
||||
// LDR/STR half imm offset
|
||||
F(MemImmHalf), F(MemImmHalf),
|
||||
// LDR/STR sp rel
|
||||
F(MemSPRel), F(MemSPRel),
|
||||
// PUSH/POP
|
||||
F(PUSH_POP), F(PUSH_POP),
|
||||
// LDMIA, STMIA
|
||||
F(LDMIA_STMIA), F(LDMIA_STMIA),
|
||||
// Branch
|
||||
F(BCOND), F(BranchXchangeReg), F(BranchXchangeReg), F(B), F(BL_LONG_1), F(BL_LONG_2),
|
||||
// Unk, SVC
|
||||
NULL, NULL,
|
||||
F(BL_Merged)
|
||||
};
|
||||
|
||||
bool Compiler::CanCompile(bool thumb, u16 kind)
|
||||
{
|
||||
return (thumb ? T_Comp[kind] : A_Comp[kind]) != NULL;
|
||||
}
|
||||
|
||||
void Compiler::Comp_BranchSpecialBehaviour()
|
||||
{
|
||||
if (CurInstr.BranchFlags & branch_IdleBranch)
|
||||
{
|
||||
MOVI2R(W0, 1);
|
||||
STRB(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, IdleLoop));
|
||||
}
|
||||
|
||||
if (CurInstr.BranchFlags & branch_FollowCondNotTaken)
|
||||
{
|
||||
SaveCPSR(false);
|
||||
RegCache.PrepareExit();
|
||||
ADD(W0, RCycles, ConstantCycles);
|
||||
ABI_PopRegisters(SavedRegs);
|
||||
RET();
|
||||
}
|
||||
}
|
||||
|
||||
JitBlockEntry Compiler::CompileBlock(ARM* cpu, bool thumb, FetchedInstr instrs[], int instrsCount)
|
||||
{
|
||||
if (JitMemUseableSize - GetCodeOffset() < 1024 * 16)
|
||||
{
|
||||
printf("JIT memory full, resetting...\n");
|
||||
ResetBlockCache();
|
||||
}
|
||||
|
||||
JitBlockEntry res = (JitBlockEntry)GetRXPtr();
|
||||
|
||||
Thumb = thumb;
|
||||
Num = cpu->Num;
|
||||
CurCPU = cpu;
|
||||
ConstantCycles = 0;
|
||||
RegCache = RegisterCache<Compiler, ARM64Reg>(this, instrs, instrsCount, true);
|
||||
|
||||
//printf("compiling block at %x\n", R15 - (Thumb ? 2 : 4));
|
||||
const u32 ALL_CALLEE_SAVED = 0x7FF80000;
|
||||
|
||||
SavedRegs = BitSet32((RegCache.GetPushRegs() | BitSet32(0x78000000)) & BitSet32(ALL_CALLEE_SAVED));
|
||||
|
||||
//if (Num == 1)
|
||||
{
|
||||
ABI_PushRegisters(SavedRegs);
|
||||
|
||||
MOVP2R(RCPU, CurCPU);
|
||||
MOVI2R(RCycles, 0);
|
||||
|
||||
LoadCPSR();
|
||||
}
|
||||
|
||||
for (int i = 0; i < instrsCount; i++)
|
||||
{
|
||||
CurInstr = instrs[i];
|
||||
R15 = CurInstr.Addr + (Thumb ? 4 : 8);
|
||||
CodeRegion = R15 >> 24;
|
||||
|
||||
CompileFunc comp = Thumb
|
||||
? T_Comp[CurInstr.Info.Kind]
|
||||
: A_Comp[CurInstr.Info.Kind];
|
||||
|
||||
Exit = i == (instrsCount - 1) || (CurInstr.BranchFlags & branch_FollowCondNotTaken);
|
||||
|
||||
//printf("%x instr %x regs: r%x w%x n%x flags: %x %x %x\n", R15, CurInstr.Instr, CurInstr.Info.SrcRegs, CurInstr.Info.DstRegs, CurInstr.Info.ReadFlags, CurInstr.Info.NotStrictlyNeeded, CurInstr.Info.WriteFlags, CurInstr.SetFlags);
|
||||
|
||||
bool isConditional = Thumb ? CurInstr.Info.Kind == ARMInstrInfo::tk_BCOND : CurInstr.Cond() < 0xE;
|
||||
if (comp == NULL || (CurInstr.BranchFlags & branch_FollowCondTaken) || (i == instrsCount - 1 && (!CurInstr.Info.Branches() || isConditional)))
|
||||
{
|
||||
MOVI2R(W0, R15);
|
||||
STR(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, R[15]));
|
||||
if (comp == NULL)
|
||||
{
|
||||
MOVI2R(W0, CurInstr.Instr);
|
||||
STR(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, CurInstr));
|
||||
}
|
||||
if (Num == 0)
|
||||
{
|
||||
MOVI2R(W0, (s32)CurInstr.CodeCycles);
|
||||
STR(INDEX_UNSIGNED, W0, RCPU, offsetof(ARM, CodeCycles));
|
||||
}
|
||||
}
|
||||
|
||||
if (comp == NULL)
|
||||
{
|
||||
SaveCPSR();
|
||||
RegCache.Flush();
|
||||
}
|
||||
else
|
||||
RegCache.Prepare(Thumb, i);
|
||||
|
||||
if (Thumb)
|
||||
{
|
||||
if (comp == NULL)
|
||||
{
|
||||
MOV(X0, RCPU);
|
||||
QuickCallFunction(X1, InterpretTHUMB[CurInstr.Info.Kind]);
|
||||
}
|
||||
else
|
||||
(this->*comp)();
|
||||
}
|
||||
else
|
||||
{
|
||||
u32 cond = CurInstr.Cond();
|
||||
if (CurInstr.Info.Kind == ARMInstrInfo::ak_BLX_IMM)
|
||||
{
|
||||
if (comp)
|
||||
(this->*comp)();
|
||||
else
|
||||
{
|
||||
MOV(X0, RCPU);
|
||||
QuickCallFunction(X1, ARMInterpreter::A_BLX_IMM);
|
||||
}
|
||||
}
|
||||
else if (cond == 0xF)
|
||||
Comp_AddCycles_C();
|
||||
else
|
||||
{
|
||||
IrregularCycles = false;
|
||||
|
||||
FixupBranch skipExecute;
|
||||
if (cond < 0xE)
|
||||
skipExecute = CheckCondition(cond);
|
||||
|
||||
if (comp == NULL)
|
||||
{
|
||||
MOV(X0, RCPU);
|
||||
QuickCallFunction(X1, InterpretARM[CurInstr.Info.Kind]);
|
||||
}
|
||||
else
|
||||
{
|
||||
(this->*comp)();
|
||||
}
|
||||
|
||||
Comp_BranchSpecialBehaviour();
|
||||
|
||||
if (cond < 0xE)
|
||||
{
|
||||
if (IrregularCycles)
|
||||
{
|
||||
FixupBranch skipNop = B();
|
||||
SetJumpTarget(skipExecute);
|
||||
|
||||
Comp_AddCycles_C();
|
||||
|
||||
if (CurInstr.BranchFlags & branch_FollowCondTaken)
|
||||
{
|
||||
SaveCPSR(false);
|
||||
RegCache.PrepareExit();
|
||||
ADD(W0, RCycles, ConstantCycles);
|
||||
ABI_PopRegisters(SavedRegs);
|
||||
RET();
|
||||
}
|
||||
|
||||
SetJumpTarget(skipNop);
|
||||
}
|
||||
else
|
||||
SetJumpTarget(skipExecute);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if (comp == NULL)
|
||||
LoadCPSR();
|
||||
}
|
||||
|
||||
RegCache.Flush();
|
||||
|
||||
//if (Num == 1)
|
||||
{
|
||||
SaveCPSR();
|
||||
|
||||
ADD(W0, RCycles, ConstantCycles);
|
||||
|
||||
ABI_PopRegisters(SavedRegs);
|
||||
}
|
||||
//else
|
||||
// ADD(RCycles, RCycles, ConstantCycles);
|
||||
|
||||
RET();
|
||||
|
||||
FlushIcache();
|
||||
|
||||
//printf("finished\n");
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
void Compiler::Reset()
|
||||
{
|
||||
SetCodePtr(0);
|
||||
|
||||
const u32 brk_0 = 0xD4200000;
|
||||
|
||||
for (int i = 0; i < JitMemUseableSize / 4; i++)
|
||||
*(((u32*)GetRWPtr()) + i) = brk_0;
|
||||
}
|
||||
|
||||
void Compiler::Comp_AddCycles_C(bool nonConst)
|
||||
{
|
||||
s32 cycles = Num ?
|
||||
NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 1 : 3]
|
||||
: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles);
|
||||
|
||||
if (!nonConst && !CurInstr.Info.Branches())
|
||||
ConstantCycles += cycles;
|
||||
else
|
||||
ADD(RCycles, RCycles, cycles);
|
||||
}
|
||||
|
||||
void Compiler::Comp_AddCycles_CI(u32 numI)
|
||||
{
|
||||
s32 cycles = (Num ?
|
||||
NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2]
|
||||
: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles)) + numI;
|
||||
|
||||
if (Thumb || CurInstr.Cond() >= 0xE)
|
||||
ConstantCycles += cycles;
|
||||
else
|
||||
ADD(RCycles, RCycles, cycles);
|
||||
}
|
||||
|
||||
void Compiler::Comp_AddCycles_CI(u32 c, ARM64Reg numI, ArithOption shift)
|
||||
{
|
||||
s32 cycles = (Num ?
|
||||
NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2]
|
||||
: ((R15 & 0x2) ? 0 : CurInstr.CodeCycles)) + c;
|
||||
|
||||
ADD(RCycles, RCycles, numI, shift);
|
||||
if (Thumb || CurInstr.Cond() >= 0xE)
|
||||
ConstantCycles += c;
|
||||
else
|
||||
ADD(RCycles, RCycles, cycles);
|
||||
}
|
||||
|
||||
void Compiler::Comp_AddCycles_CDI()
|
||||
{
|
||||
if (Num == 0)
|
||||
Comp_AddCycles_CD();
|
||||
else
|
||||
{
|
||||
IrregularCycles = true;
|
||||
|
||||
s32 cycles;
|
||||
|
||||
s32 numC = NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
|
||||
s32 numD = CurInstr.DataCycles;
|
||||
|
||||
if (CurInstr.DataRegion == 0x02) // mainRAM
|
||||
{
|
||||
if (CodeRegion == 0x02)
|
||||
cycles = numC + numD;
|
||||
else
|
||||
{
|
||||
numC++;
|
||||
cycles = std::max(numC + numD - 3, std::max(numC, numD));
|
||||
}
|
||||
}
|
||||
else if (CodeRegion == 0x02)
|
||||
{
|
||||
numD++;
|
||||
cycles = std::max(numC + numD - 3, std::max(numC, numD));
|
||||
}
|
||||
else
|
||||
{
|
||||
cycles = numC + numD + 1;
|
||||
}
|
||||
|
||||
if (!Thumb && CurInstr.Cond() < 0xE)
|
||||
ADD(RCycles, RCycles, cycles);
|
||||
else
|
||||
ConstantCycles += cycles;
|
||||
}
|
||||
}
|
||||
|
||||
void Compiler::Comp_AddCycles_CD()
|
||||
{
|
||||
u32 cycles = 0;
|
||||
if (Num == 0)
|
||||
{
|
||||
s32 numC = (R15 & 0x2) ? 0 : CurInstr.CodeCycles;
|
||||
s32 numD = CurInstr.DataCycles;
|
||||
|
||||
//if (DataRegion != CodeRegion)
|
||||
cycles = std::max(numC + numD - 6, std::max(numC, numD));
|
||||
|
||||
IrregularCycles = cycles != numC;
|
||||
}
|
||||
else
|
||||
{
|
||||
s32 numC = NDS::ARM7MemTimings[CurInstr.CodeCycles][Thumb ? 0 : 2];
|
||||
s32 numD = CurInstr.DataCycles;
|
||||
|
||||
if (CurInstr.DataRegion == 0x02)
|
||||
{
|
||||
if (CodeRegion == 0x02)
|
||||
cycles += numC + numD;
|
||||
else
|
||||
cycles += std::max(numC + numD - 3, std::max(numC, numD));
|
||||
}
|
||||
else if (CodeRegion == 0x02)
|
||||
{
|
||||
cycles += std::max(numC + numD - 3, std::max(numC, numD));
|
||||
}
|
||||
else
|
||||
{
|
||||
cycles += numC + numD;
|
||||
}
|
||||
|
||||
IrregularCycles = true;
|
||||
}
|
||||
|
||||
if ((!Thumb && CurInstr.Cond() < 0xE) && IrregularCycles)
|
||||
ADD(RCycles, RCycles, cycles);
|
||||
else
|
||||
ConstantCycles += cycles;
|
||||
}
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user