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https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
fix some gaps in CPU modes
* non-defined CPU modes are actually possible * bit4 of all PSRs is forced to one (modes 00-0F aren't possible) * modes 14/15/16 and 18/19/1A share a SPSR with modes 17 and 1B respectively (but they don't share the register banks) * modes 10 and 1C/1D/1E don't have a SPSR (MRS returns the CPSR always)
This commit is contained in:
24
src/ARM.cpp
24
src/ARM.cpp
@ -109,6 +109,22 @@ void ARM::Reset()
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CPSR = 0x000000D3;
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for (int i = 0; i < 7; i++)
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R_FIQ[i] = 0;
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for (int i = 0; i < 2; i++)
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{
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R_SVC[i] = 0;
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R_ABT[i] = 0;
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R_IRQ[i] = 0;
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R_UND[i] = 0;
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}
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R_FIQ[7] = 0x00000010;
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R_SVC[2] = 0x00000010;
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R_ABT[2] = 0x00000010;
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R_IRQ[2] = 0x00000010;
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R_UND[2] = 0x00000010;
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ExceptionBase = Num ? 0x00000000 : 0xFFFF0000;
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CodeMem.Mem = NULL;
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@ -375,10 +391,16 @@ void ARM::RestoreCPSR()
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CPSR = R_SVC[2];
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break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17:
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CPSR = R_ABT[2];
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break;
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B:
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CPSR = R_UND[2];
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break;
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@ -388,6 +410,8 @@ void ARM::RestoreCPSR()
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break;
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}
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CPSR |= 0x00000010;
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UpdateMode(oldcpsr, CPSR);
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}
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