mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-21 05:09:46 -06:00
fix some gaps in CPU modes
* non-defined CPU modes are actually possible * bit4 of all PSRs is forced to one (modes 00-0F aren't possible) * modes 14/15/16 and 18/19/1A share a SPSR with modes 17 and 1B respectively (but they don't share the register banks) * modes 10 and 1C/1D/1E don't have a SPSR (MRS returns the CPSR always)
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@ -69,9 +69,17 @@ void A_MSR_IMM(ARM* cpu)
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case 0x11: psr = &cpu->R_FIQ[7]; break;
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case 0x12: psr = &cpu->R_IRQ[2]; break;
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case 0x13: psr = &cpu->R_SVC[2]; break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17: psr = &cpu->R_ABT[2]; break;
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B: psr = &cpu->R_UND[2]; break;
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default: printf("bad CPU mode %08X\n", cpu->CPSR); return;
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default:
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cpu->AddCycles_C();
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return;
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}
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}
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else
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@ -92,6 +100,9 @@ void A_MSR_IMM(ARM* cpu)
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u32 val = ROR((cpu->CurInstr & 0xFF), ((cpu->CurInstr >> 7) & 0x1E));
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// bit4 is forced to 1
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val |= 0x00000010;
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*psr &= ~mask;
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*psr |= (val & mask);
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@ -111,9 +122,17 @@ void A_MSR_REG(ARM* cpu)
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case 0x11: psr = &cpu->R_FIQ[7]; break;
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case 0x12: psr = &cpu->R_IRQ[2]; break;
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case 0x13: psr = &cpu->R_SVC[2]; break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17: psr = &cpu->R_ABT[2]; break;
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B: psr = &cpu->R_UND[2]; break;
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default: printf("bad CPU mode %08X\n", cpu->CPSR); return;
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default:
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cpu->AddCycles_C();
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return;
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}
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}
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else
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@ -134,6 +153,9 @@ void A_MSR_REG(ARM* cpu)
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u32 val = cpu->R[cpu->CurInstr & 0xF];
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// bit4 is forced to 1
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val |= 0x00000010;
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*psr &= ~mask;
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*psr |= (val & mask);
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@ -153,9 +175,15 @@ void A_MRS(ARM* cpu)
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case 0x11: psr = cpu->R_FIQ[7]; break;
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case 0x12: psr = cpu->R_IRQ[2]; break;
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case 0x13: psr = cpu->R_SVC[2]; break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17: psr = cpu->R_ABT[2]; break;
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B: psr = cpu->R_UND[2]; break;
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default: printf("bad CPU mode %08X\n", cpu->CPSR); return;
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default: psr = cpu->CPSR; break;
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}
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}
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else
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