fix some gaps in CPU modes

* non-defined CPU modes are actually possible
* bit4 of all PSRs is forced to one (modes 00-0F aren't possible)
* modes 14/15/16 and 18/19/1A share a SPSR with modes 17 and 1B respectively (but they don't share the register banks)
* modes 10 and 1C/1D/1E don't have a SPSR (MRS returns the CPSR always)
This commit is contained in:
Arisotura
2021-10-28 19:45:32 +02:00
parent ae489d9e03
commit 9d82826cdb
2 changed files with 55 additions and 3 deletions

View File

@ -69,9 +69,17 @@ void A_MSR_IMM(ARM* cpu)
case 0x11: psr = &cpu->R_FIQ[7]; break;
case 0x12: psr = &cpu->R_IRQ[2]; break;
case 0x13: psr = &cpu->R_SVC[2]; break;
case 0x14:
case 0x15:
case 0x16:
case 0x17: psr = &cpu->R_ABT[2]; break;
case 0x18:
case 0x19:
case 0x1A:
case 0x1B: psr = &cpu->R_UND[2]; break;
default: printf("bad CPU mode %08X\n", cpu->CPSR); return;
default:
cpu->AddCycles_C();
return;
}
}
else
@ -92,6 +100,9 @@ void A_MSR_IMM(ARM* cpu)
u32 val = ROR((cpu->CurInstr & 0xFF), ((cpu->CurInstr >> 7) & 0x1E));
// bit4 is forced to 1
val |= 0x00000010;
*psr &= ~mask;
*psr |= (val & mask);
@ -111,9 +122,17 @@ void A_MSR_REG(ARM* cpu)
case 0x11: psr = &cpu->R_FIQ[7]; break;
case 0x12: psr = &cpu->R_IRQ[2]; break;
case 0x13: psr = &cpu->R_SVC[2]; break;
case 0x14:
case 0x15:
case 0x16:
case 0x17: psr = &cpu->R_ABT[2]; break;
case 0x18:
case 0x19:
case 0x1A:
case 0x1B: psr = &cpu->R_UND[2]; break;
default: printf("bad CPU mode %08X\n", cpu->CPSR); return;
default:
cpu->AddCycles_C();
return;
}
}
else
@ -134,6 +153,9 @@ void A_MSR_REG(ARM* cpu)
u32 val = cpu->R[cpu->CurInstr & 0xF];
// bit4 is forced to 1
val |= 0x00000010;
*psr &= ~mask;
*psr |= (val & mask);
@ -153,9 +175,15 @@ void A_MRS(ARM* cpu)
case 0x11: psr = cpu->R_FIQ[7]; break;
case 0x12: psr = cpu->R_IRQ[2]; break;
case 0x13: psr = cpu->R_SVC[2]; break;
case 0x14:
case 0x15:
case 0x16:
case 0x17: psr = cpu->R_ABT[2]; break;
case 0x18:
case 0x19:
case 0x1A:
case 0x1B: psr = cpu->R_UND[2]; break;
default: printf("bad CPU mode %08X\n", cpu->CPSR); return;
default: psr = cpu->CPSR; break;
}
}
else