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tweak when irqs are triggered and fix prefetch aborts

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also ig add some comments next to the svc funcs so that someone searching for "swi" can find them easier
This commit is contained in:
Jaklyy 2024-08-05 14:57:17 -04:00
parent eedd2806f9
commit a85b2bfb56
2 changed files with 23 additions and 22 deletions
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35
src/ARM.cpp
View File

@ -548,7 +548,7 @@ void ARM::TriggerIRQ()
UpdateMode(oldcpsr, CPSR); UpdateMode(oldcpsr, CPSR);
R_IRQ[2] = oldcpsr; R_IRQ[2] = oldcpsr;
R[14] = R[15] + (oldcpsr & 0x20 ? 2 : 0); R[14] = R[15] - (oldcpsr & 0x20 ? 0 : 4);
JumpTo(ExceptionBase + 0x18); JumpTo(ExceptionBase + 0x18);
// ARDS cheat support // ARDS cheat support
@ -570,7 +570,7 @@ void ARMv5::PrefetchAbort()
UpdateMode(oldcpsr, CPSR); UpdateMode(oldcpsr, CPSR);
R_ABT[2] = oldcpsr; R_ABT[2] = oldcpsr;
R[14] = R[15] + (oldcpsr & 0x20 ? 2 : 0); R[14] = R[15] - (oldcpsr & 0x20 ? 0 : 4);
JumpTo(ExceptionBase + 0x0C); JumpTo(ExceptionBase + 0x0C);
} }
@ -609,7 +609,7 @@ void ARMv5::Execute()
{ {
Halted = 0; Halted = 0;
if (NDS.IME[0] & 0x1) if (NDS.IME[0] & 0x1)
TriggerIRQ(); IRQ = 1;
} }
else else
{ {
@ -671,13 +671,13 @@ void ARMv5::Execute()
if (R[15] & 0x2) { NextInstr[1] >>= 16; CodeCycles = 0; } if (R[15] & 0x2) { NextInstr[1] >>= 16; CodeCycles = 0; }
else NextInstr[1] = CodeRead32(R[15], false); else NextInstr[1] = CodeRead32(R[15], false);
// handle aborted instructions
if (!(PU_Map[(R[15]-4)>>12] & 0x04)) [[unlikely]] if (IRQ && !(CPSR & 0x80)) TriggerIRQ();
else if (!(PU_Map[(R[15]-4)>>12] & 0x04)) [[unlikely]] // handle aborted instructions
{ {
PrefetchAbort(); PrefetchAbort();
} }
// actually execute else [[likely]] // actually execute
else [[likely]]
{ {
u32 icode = (CurInstr >> 6) & 0x3FF; u32 icode = (CurInstr >> 6) & 0x3FF;
ARMInterpreter::THUMBInstrTable[icode](this); ARMInterpreter::THUMBInstrTable[icode](this);
@ -694,13 +694,13 @@ void ARMv5::Execute()
NextInstr[0] = NextInstr[1]; NextInstr[0] = NextInstr[1];
NextInstr[1] = CodeRead32(R[15], false); NextInstr[1] = CodeRead32(R[15], false);
// handle aborted instructions
if (!(PU_Map[(R[15]-8)>>12] & 0x04)) [[unlikely]] // todo: check for bkpt instruction? if (IRQ && !(CPSR & 0x80)) TriggerIRQ();
else if (!(PU_Map[(R[15]-8)>>12] & 0x04)) [[unlikely]] // handle aborted instructions
{ {
PrefetchAbort(); PrefetchAbort();
} }
// actually execute else if (CheckCondition(CurInstr >> 28)) [[likely]] // actually execute
else if (CheckCondition(CurInstr >> 28)) [[likely]]
{ {
u32 icode = ((CurInstr >> 4) & 0xF) | ((CurInstr >> 16) & 0xFF0); u32 icode = ((CurInstr >> 4) & 0xF) | ((CurInstr >> 16) & 0xFF0);
ARMInterpreter::ARMInstrTable[icode](this); ARMInterpreter::ARMInstrTable[icode](this);
@ -727,8 +727,6 @@ void ARMv5::Execute()
if (NDS::IME[0] & 0x1) if (NDS::IME[0] & 0x1)
TriggerIRQ(); TriggerIRQ();
}*/ }*/
if (IRQ) TriggerIRQ();
} }
NDS.ARM9Timestamp += Cycles; NDS.ARM9Timestamp += Cycles;
@ -760,7 +758,7 @@ void ARMv4::Execute()
{ {
Halted = 0; Halted = 0;
if (NDS.IME[1] & 0x1) if (NDS.IME[1] & 0x1)
TriggerIRQ(); IRQ = 1;
} }
else else
{ {
@ -820,10 +818,14 @@ void ARMv4::Execute()
NextInstr[0] = NextInstr[1]; NextInstr[0] = NextInstr[1];
NextInstr[1] = CodeRead16(R[15]); NextInstr[1] = CodeRead16(R[15]);
if (IRQ && !(CPSR & 0x80)) TriggerIRQ();
else
{
// actually execute // actually execute
u32 icode = (CurInstr >> 6); u32 icode = (CurInstr >> 6);
ARMInterpreter::THUMBInstrTable[icode](this); ARMInterpreter::THUMBInstrTable[icode](this);
} }
}
else else
{ {
if constexpr (mode == CPUExecuteMode::InterpreterGDB) if constexpr (mode == CPUExecuteMode::InterpreterGDB)
@ -835,8 +837,8 @@ void ARMv4::Execute()
NextInstr[0] = NextInstr[1]; NextInstr[0] = NextInstr[1];
NextInstr[1] = CodeRead32(R[15]); NextInstr[1] = CodeRead32(R[15]);
// actually execute if (IRQ && !(CPSR & 0x80)) TriggerIRQ();
if (CheckCondition(CurInstr >> 28)) else if (CheckCondition(CurInstr >> 28)) // actually execute
{ {
u32 icode = ((CurInstr >> 4) & 0xF) | ((CurInstr >> 16) & 0xFF0); u32 icode = ((CurInstr >> 4) & 0xF) | ((CurInstr >> 16) & 0xFF0);
ARMInterpreter::ARMInstrTable[icode](this); ARMInterpreter::ARMInstrTable[icode](this);
@ -859,7 +861,6 @@ void ARMv4::Execute()
if (NDS::IME[1] & 0x1) if (NDS::IME[1] & 0x1)
TriggerIRQ(); TriggerIRQ();
}*/ }*/
if (IRQ) TriggerIRQ();
} }
NDS.ARM7Timestamp += Cycles; NDS.ARM7Timestamp += Cycles;

4
src/ARMInterpreter.cpp
View File

@ -271,7 +271,7 @@ void A_MRC(ARM* cpu)
void A_SVC(ARM* cpu) void A_SVC(ARM* cpu) // A_SWI
{ {
u32 oldcpsr = cpu->CPSR; u32 oldcpsr = cpu->CPSR;
cpu->CPSR &= ~0xBF; cpu->CPSR &= ~0xBF;
@ -283,7 +283,7 @@ void A_SVC(ARM* cpu)
cpu->JumpTo(cpu->ExceptionBase + 0x08); cpu->JumpTo(cpu->ExceptionBase + 0x08);
} }
void T_SVC(ARM* cpu) void T_SVC(ARM* cpu) // T_SWI
{ {
u32 oldcpsr = cpu->CPSR; u32 oldcpsr = cpu->CPSR;
cpu->CPSR &= ~0xBF; cpu->CPSR &= ~0xBF;