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initial implementation of interlock cycles

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Jaklyy
2024-06-15 16:07:36 -04:00
parent aa1217af0a
commit a973c0bf5b
5 changed files with 179 additions and 125 deletions
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4
src/ARMInterpreter.cpp
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@ -163,7 +163,7 @@ void A_MSR_REG(ARM* cpu)
if ((cpu->CPSR & 0x1F) == 0x10) mask &= 0xFFFFFF00;
u32 val = cpu->R[cpu->CurInstr & 0xF];
u32 val = cpu->GetReg(cpu->CurInstr & 0xF, 1);
// bit4 is forced to 1
val |= 0x00000010;
@ -216,7 +216,7 @@ void A_MCR(ARM* cpu)
u32 cn = (cpu->CurInstr >> 16) & 0xF;
u32 cm = cpu->CurInstr & 0xF;
u32 cpinfo = (cpu->CurInstr >> 5) & 0x7;
u32 val = cpu->R[(cpu->CurInstr>>12)&0xF];
u32 val = cpu->GetReg((cpu->CurInstr>>12)&0xF);
if (((cpu->CurInstr>>12) & 0xF) == 15) val += 4;
if (cpu->Num==0 && cp==15)