piwalker/melonDS
1
0
Fork 0
mirror of https://github.com/melonDS-emu/melonDS.git synced 2025-07-26 07:39:56 -06:00
Code Issues Packages Projects Releases Wiki Activity

revert timing tweaks, finish thumb interwork code

Browse Source
This commit is contained in:
Jaklyy
2024-08-04 14:45:28 -04:00
parent 4b703d24b5
commit ab2a8f128f
4 changed files with 83 additions and 212 deletions
Download Patch File Download Diff File Expand all files Collapse all files

126
src/ARM.cpp
View File

@ -300,9 +300,6 @@ void ARMv5::JumpTo(u32 addr, bool restorecpsr)
u32 oldregion = R[15] >> 24;
u32 newregion = addr >> 24;
if (addr < ITCMSize) CodeRegion = Mem9_ITCM;
else CodeRegion = NDS.ARM9Regions[addr >> 14];
RegionCodeCycles = MemTimings[addr >> 12][0];
@ -644,7 +641,7 @@ void ARMv5::Execute()
R[15] += 2;
CurInstr = NextInstr[0];
NextInstr[0] = NextInstr[1];
if (R[15] & 0x2) { NextInstr[1] >>= 16; CodeCycles = 1; }
if (R[15] & 0x2) { NextInstr[1] >>= 16; CodeCycles = 0; }
else NextInstr[1] = CodeRead32(R[15], false);
// actually execute
@ -1256,127 +1253,6 @@ bool ARMv4::DataWrite32S(u32 addr, u32 val, bool dataabort)
}
void ARMv5::AddCycles_CD_STR()
{
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
s32 early;
if (DataRegion == Mem9_ITCM)
{
early = (CodeRegion == Mem9_ITCM) ? 0 : 2;
}
else if (DataRegion == Mem9_DTCM)
{
early = 2;
}
else if (DataRegion == Mem9_MainRAM)
{
early = (CodeRegion == Mem9_MainRAM) ? 0 : 18; // CHECKME: how early can main ram be?
}
else early = (DataRegion == CodeRegion) ? 4 : 6;
s32 code = numC - early;
if (code < 0) code = 0;
Cycles += std::max(code + numD, numC);
}
void ARMv5::AddCycles_CD_STM()
{
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
s32 early;
if (DataRegion == Mem9_ITCM)
{
early = (CodeRegion == Mem9_ITCM) ? -1 : 0; // stm adds either: no penalty or benefit to itcm loads, or a 1 cycle penalty if executing from itcm.
}
else if (DataRegion == Mem9_DTCM)
{
early = 2;
}
else if (DataRegion == Mem9_MainRAM)
{
early = (CodeRegion == Mem9_MainRAM) ? 0 : 18; // CHECKME: how early can main ram be?
}
else early = (DataRegion == CodeRegion) ? 4 : 6;
s32 code = numC - early;
if (code < 0) code = 0;
Cycles += std::max(code + numD, numC);
}
void ARMv5::AddCycles_CDI_LDR()
{
// LDR cycles. ARM9 seems to skip the internal cycle here.
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
// if a 32 bit bus, start 2 cycles early; else, start 4 cycles early
s32 early;
if (DataRegion == Mem9_ITCM)
{
early = (CodeRegion == Mem9_ITCM) ? 0 : 2;
}
else if (DataRegion == Mem9_DTCM)
{
early = 2;
}
else if (DataRegion == Mem9_MainRAM)
{
early = (CodeRegion == Mem9_MainRAM) ? 0 : 6;
}
else early = 6;
s32 code = numC - early;
if (code < 0) code = 0;
Cycles += std::max(code + numD, numC);
}
void ARMv5::AddCycles_CDI_LDM()
{
// LDM cycles. ARM9 seems to skip the internal cycle here.
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
// if a 32 bit bus, start 2 cycles early; else, start 4 cycles early
s32 early;
switch (DataRegion)
{
case 0: // background region;
case Mem9_DTCM:
case Mem9_BIOS:
case Mem9_WRAM:
case Mem9_IO:
case Mem9_Pal: // CHECKME
default:
early = 2;
break;
case Mem9_OAM: // CHECKME
case Mem9_GBAROM:
case Mem9_GBARAM:
early = 4;
break;
case Mem9_MainRAM:
early = (CodeRegion == Mem9_MainRAM) ? 0 : 4;
break;
case Mem9_VRAM: // the dsi can toggle the bus width of vram between 32 and 16 bit
early = (NDS.ConsoleType == 0 || !(((DSi&)NDS).SCFG_EXT[0] & (1<<13))) ? 4 : 2;
break;
case Mem9_ITCM: // itcm data fetches cannot be done at the same time as a code fetch, it'll even incurr a 1 cycle penalty when executing from itcm
early = (CodeRegion == Mem9_ITCM) ? -1 : 0;
break;
}
s32 code = numC - early;
if (code < 0) code = 0;
Cycles += std::max(code + numD, numC);
}
void ARMv4::AddCycles_C()
{
// code only. this code fetch is sequential.