mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
some attempt at cart support
This commit is contained in:
StapleButter
239
NDS.cpp
239
NDS.cpp
@ -21,6 +21,7 @@
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#include "NDS.h"
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#include "ARM.h"
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#include "CP15.h"
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#include "NDSCart.h"
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#include "DMA.h"
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#include "FIFO.h"
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#include "GPU.h"
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@ -28,12 +29,6 @@
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#include "RTC.h"
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#include "Wifi.h"
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// derp
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namespace SPI_Firmware
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{
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extern u8* Firmware;
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}
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namespace NDS
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{
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@ -74,6 +69,11 @@ u32 ARM9ITCMSize;
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u8 ARM9DTCM[0x4000];
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u32 ARM9DTCMBase, ARM9DTCMSize;
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u16 ExMemCnt[2];
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u8 ROMSeed0[2*8];
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u8 ROMSeed1[2*8];
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// IO shit
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u32 IME[2];
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u32 IE[2], IF[2];
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@ -99,12 +99,6 @@ u32 DivDenominator[2];
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u32 DivQuotient[2];
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u32 DivRemainder[2];
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u32 ROMSPIControl;
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u32 ROMControl;
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u8 ROMCommand[8];
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u8 ROMCurCommand[8];
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u32 ROMReadPos, ROMReadSize;
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u32 KeyInput;
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u16 _soundbias; // temp
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@ -129,6 +123,7 @@ void Init()
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IPCFIFO9 = new FIFO(16);
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IPCFIFO7 = new FIFO(16);
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NDSCart::Init();
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GPU::Init();
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SPI::Init();
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RTC::Init();
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@ -220,6 +215,11 @@ void Reset()
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ARM9DTCMBase = 0xFFFFFFFF;
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ARM9DTCMSize = 0;
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ExMemCnt[0] = 0;
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ExMemCnt[1] = 0;
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memset(ROMSeed0, 0, 2*8);
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memset(ROMSeed1, 0, 2*8);
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IME[0] = 0;
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IME[1] = 0;
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@ -237,10 +237,6 @@ void Reset()
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DivCnt = 0;
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ROMSPIControl = 0;
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ROMControl = 0;
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memset(ROMCommand, 0, 8);
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ARM9->Reset();
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ARM7->Reset();
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CP15::Reset();
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@ -250,6 +246,7 @@ void Reset()
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for (i = 0; i < 8; i++) DMAs[i]->Reset();
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memset(DMA9Fill, 0, 4*4);
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NDSCart::Reset();
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GPU::Reset();
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SPI::Reset();
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RTC::Reset();
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@ -269,6 +266,7 @@ void Reset()
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// test
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//LoadROM();
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//LoadFirmware();
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NDSCart::LoadROM("rom/nsmb.nds");
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Running = true; // hax
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}
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@ -512,6 +510,17 @@ bool HaltInterrupted(u32 cpu)
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void CheckDMAs(u32 cpu, u32 mode)
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{
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cpu <<= 2;
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DMAs[cpu+0]->StartIfNeeded(mode);
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DMAs[cpu+1]->StartIfNeeded(mode);
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DMAs[cpu+2]->StartIfNeeded(mode);
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DMAs[cpu+3]->StartIfNeeded(mode);
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}
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const s32 TimerPrescaler[4] = {2, 128, 512, 2048};
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void TimerIncrement(u32 param)
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@ -579,78 +588,6 @@ void TimerStart(u32 id, u16 cnt)
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void ROMEndTransfer(u32 cpu)
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{
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ROMControl &= ~(1<<23);
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ROMControl &= ~(1<<31);
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if (ROMSPIControl & (1<<14))
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TriggerIRQ(cpu, IRQ_CartSendDone);
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}
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void ROMStartTransfer(u32 cpu)
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{
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u32 datasize = (ROMControl >> 24) & 0x7;
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if (datasize == 7)
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datasize = 4;
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else if (datasize > 0)
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datasize = 0x100 << datasize;
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//datasize += (ROMControl & 0x1FFF); // KEY1 gap
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ROMReadPos = 0;
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ROMReadSize = datasize;
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*(u32*)&ROMCurCommand[0] = *(u32*)&ROMCommand[0];
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*(u32*)&ROMCurCommand[4] = *(u32*)&ROMCommand[4];
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printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n",
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ROMSPIControl, ROMControl,
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ROMCommand[0], ROMCommand[1], ROMCommand[2], ROMCommand[3],
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ROMCommand[4], ROMCommand[5], ROMCommand[6], ROMCommand[7],
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datasize);
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ROMControl |= (1<<23);
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if (datasize == 0)
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{
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// hax
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/*if (ROMCommand[0] == 0xBA)
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ScheduleEvent(0x910*5*2, ROMEndTransfer, cpu);
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else*/
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ROMEndTransfer(cpu);
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printf("ROM transfer done. %08X %08X\n", ARM7Read32(0x03FFFFF8), ARM7Read32(0x03FFFFFC));
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}
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}
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u32 ROMReadData(u32 cpu)
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{
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u32 ret = 0;
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switch (ROMCurCommand[0])
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{
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case 0x9F: ret = 0xFFFFFFFF; break;
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case 0x00:
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// TODO: feed an actual cart header!
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ret = 0;
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break;
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case 0x90:
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// chip ID
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ret = 0;
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break;
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}
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ROMReadPos += 4;
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if (ROMReadPos >= ROMReadSize)
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ROMEndTransfer(cpu);
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return ret;
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}
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void StartDiv()
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{
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// TODO: division isn't instant!
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@ -1398,8 +1335,9 @@ u16 ARM9IORead16(u32 addr)
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return val;
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}
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case 0x04000204: return 0;//0xFFFF;
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case 0x040001A0: return NDSCart::SPICnt;
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case 0x04000204: return ExMemCnt[0];
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case 0x04000208: return IME[0];
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case 0x04000280: return DivCnt;
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@ -1450,6 +1388,8 @@ u32 ARM9IORead32(u32 addr)
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case 0x04000108: return Timers[2].Counter | (Timers[2].Control << 16);
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case 0x0400010C: return Timers[3].Counter | (Timers[3].Control << 16);
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case 0x040001A4: return NDSCart::ROMCnt;
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case 0x04000208: return IME[0];
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case 0x04000210: return IE[0];
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case 0x04000214: return IF[0];
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@ -1483,6 +1423,10 @@ u32 ARM9IORead32(u32 addr)
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}
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else
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return IPCFIFO7->Peek();
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case 0x04100010:
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if (!(ExMemCnt[0] & (1<<11))) return NDSCart::ReadData();
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return 0;
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}
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if (addr >= 0x04000000 && addr < 0x04000060)
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@ -1503,14 +1447,29 @@ void ARM9IOWrite8(u32 addr, u8 val)
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switch (addr)
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{
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case 0x040001A0:
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ROMSPIControl &= 0xFF00;
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ROMSPIControl |= val;
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if (!(ExMemCnt[0] & (1<<11)))
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{
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NDSCart::SPICnt &= 0xFF00;
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NDSCart::SPICnt |= val;
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}
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return;
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case 0x040001A1:
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ROMSPIControl &= 0x00FF;
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ROMSPIControl |= (val << 8);
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if (!(ExMemCnt[0] & (1<<11)))
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{
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NDSCart::SPICnt &= 0x00FF;
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NDSCart::SPICnt |= (val << 8);
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}
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return;
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case 0x040001A8: NDSCart::ROMCommand[0] = val; return;
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case 0x040001A9: NDSCart::ROMCommand[1] = val; return;
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case 0x040001AA: NDSCart::ROMCommand[2] = val; return;
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case 0x040001AB: NDSCart::ROMCommand[3] = val; return;
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case 0x040001AC: NDSCart::ROMCommand[4] = val; return;
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case 0x040001AD: NDSCart::ROMCommand[5] = val; return;
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case 0x040001AE: NDSCart::ROMCommand[6] = val; return;
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case 0x040001AF: NDSCart::ROMCommand[7] = val; return;
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case 0x04000208: IME[0] = val & 0x1; return;
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case 0x04000240: GPU::MapVRAM_AB(0, val); return;
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@ -1584,7 +1543,15 @@ void ARM9IOWrite16(u32 addr, u16 val)
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return;
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case 0x040001A0:
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ROMSPIControl = val;
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if (!(ExMemCnt[0] & (1<<11))) NDSCart::SPICnt = val;
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return;
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case 0x040001B8: ROMSeed0[4] = val & 0x7F; return;
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case 0x040001BA: ROMSeed1[4] = val & 0x7F; return;
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case 0x04000204:
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ExMemCnt[0] = val;
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ExMemCnt[1] = (ExMemCnt[1] & 0x007F) | (val & 0xFF80);
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return;
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case 0x04000208: IME[0] = val & 0x1; return;
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@ -1689,15 +1656,19 @@ void ARM9IOWrite32(u32 addr, u32 val)
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return;
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case 0x040001A0:
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ROMSPIControl = val & 0xFFFF;
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// TODO: SPI shit
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if (!(ExMemCnt[0] & (1<<11)))
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{
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NDSCart::SPICnt = val & 0xFFFF;
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// TODO: SPI shit
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}
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return;
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case 0x040001A4:
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val &= ~0x00800000;
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ROMControl = val;
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if (val & 0x80000000) ROMStartTransfer(0);
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if (!(ExMemCnt[0] & (1<<11))) NDSCart::WriteCnt(val);
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return;
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case 0x040001B0: *(u32*)&ROMSeed0[0] = val; return;
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case 0x040001B4: *(u32*)&ROMSeed1[0] = val; return;
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case 0x04000208: IME[0] = val & 0x1; return;
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case 0x04000210: IE[0] = val; if (val&~0x000F0F7D)printf("unusual IRQ %08X\n",val);return;
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case 0x04000214: IF[0] &= ~val; return;
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@ -1754,10 +1725,6 @@ u8 ARM7IORead8(u32 addr)
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case 0x04000241: return WRAMCnt;
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case 0x04000300: return PostFlag7;
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//case 0x04000403:
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//Halt();
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//return 0;
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}
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if (addr >= 0x04000400 && addr < 0x04000520)
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@ -1803,9 +1770,12 @@ u16 ARM7IORead16(u32 addr)
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return val;
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}
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case 0x040001A0: return NDSCart::SPICnt;
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case 0x040001C0: return SPI::ReadCnt();
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case 0x040001C2: return SPI::ReadData();
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case 0x04000204: return ExMemCnt[1];
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case 0x04000208: return IME[1];
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case 0x04000300: return PostFlag7;
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@ -1848,8 +1818,7 @@ u32 ARM7IORead32(u32 addr)
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case 0x04000108: return Timers[6].Counter | (Timers[6].Control << 16);
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case 0x0400010C: return Timers[7].Counter | (Timers[7].Control << 16);
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case 0x040001A4:
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return ROMControl;
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case 0x040001A4: return NDSCart::ROMCnt;
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case 0x040001C0:
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return SPI::ReadCnt() | (SPI::ReadData() << 16);
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@ -1879,7 +1848,9 @@ u32 ARM7IORead32(u32 addr)
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else
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return IPCFIFO9->Peek();
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case 0x04100010: return ROMReadData(1);
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case 0x04100010:
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if (ExMemCnt[0] & (1<<11)) return NDSCart::ReadData();
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return 0;
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}
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if (addr >= 0x04000400 && addr < 0x04000520)
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@ -1899,22 +1870,28 @@ void ARM7IOWrite8(u32 addr, u8 val)
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case 0x04000138: RTC::Write(val, true); return;
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case 0x040001A0:
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ROMSPIControl &= 0xFF00;
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ROMSPIControl |= val;
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if (ExMemCnt[0] & (1<<11))
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{
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NDSCart::SPICnt &= 0xFF00;
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NDSCart::SPICnt |= val;
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}
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return;
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case 0x040001A1:
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ROMSPIControl &= 0x00FF;
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ROMSPIControl |= (val << 8);
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if (ExMemCnt[0] & (1<<11))
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{
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NDSCart::SPICnt &= 0x00FF;
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NDSCart::SPICnt |= (val << 8);
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}
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return;
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case 0x040001A8: ROMCommand[0] = val; return;
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case 0x040001A9: ROMCommand[1] = val; return;
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case 0x040001AA: ROMCommand[2] = val; return;
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case 0x040001AB: ROMCommand[3] = val; return;
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case 0x040001AC: ROMCommand[4] = val; return;
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case 0x040001AD: ROMCommand[5] = val; return;
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case 0x040001AE: ROMCommand[6] = val; return;
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case 0x040001AF: ROMCommand[7] = val; return;
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case 0x040001A8: NDSCart::ROMCommand[0] = val; return;
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case 0x040001A9: NDSCart::ROMCommand[1] = val; return;
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case 0x040001AA: NDSCart::ROMCommand[2] = val; return;
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case 0x040001AB: NDSCart::ROMCommand[3] = val; return;
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case 0x040001AC: NDSCart::ROMCommand[4] = val; return;
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case 0x040001AD: NDSCart::ROMCommand[5] = val; return;
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case 0x040001AE: NDSCart::ROMCommand[6] = val; return;
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case 0x040001AF: NDSCart::ROMCommand[7] = val; return;
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case 0x040001C2:
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SPI::WriteData(val);
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@ -1986,9 +1963,13 @@ void ARM7IOWrite16(u32 addr, u16 val)
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return;
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case 0x040001A0:
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ROMSPIControl = val;
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if (ExMemCnt[0] & (1<<11))
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NDSCart::SPICnt = val;
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return;
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case 0x040001B8: ROMSeed0[12] = val & 0x7F; return;
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case 0x040001BA: ROMSeed1[12] = val & 0x7F; return;
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case 0x040001C0:
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SPI::WriteCnt(val);
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return;
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@ -1997,6 +1978,10 @@ void ARM7IOWrite16(u32 addr, u16 val)
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SPI::WriteData(val & 0xFF);
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return;
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case 0x04000204:
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ExMemCnt[1] = (ExMemCnt[1] & 0xFF80) | (val & 0x007F);
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return;
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case 0x04000208: IME[1] = val & 0x1; return;
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case 0x04000300:
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@ -2008,7 +1993,7 @@ void ARM7IOWrite16(u32 addr, u16 val)
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case 0x04000304: PowerControl7 = val; return;
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case 0x04000504:
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case 0x04000504: // removeme
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_soundbias = val & 0x3FF;
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return;
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}
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@ -2072,15 +2057,19 @@ void ARM7IOWrite32(u32 addr, u32 val)
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return;
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case 0x040001A0:
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ROMSPIControl = val & 0xFFFF;
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// TODO: SPI shit
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if (ExMemCnt[0] & (1<<11))
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{
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NDSCart::SPICnt = val & 0xFFFF;
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// TODO: SPI shit
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}
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return;
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case 0x040001A4:
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val &= ~0x00800000;
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ROMControl = val;
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if (val & 0x80000000) ROMStartTransfer(1);
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if (ExMemCnt[0] & (1<<11)) NDSCart::WriteCnt(val);
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return;
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case 0x040001B0: *(u32*)&ROMSeed0[8] = val; return;
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case 0x040001B4: *(u32*)&ROMSeed1[8] = val; return;
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case 0x04000208: IME[1] = val & 0x1; return;
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case 0x04000210: IE[1] = val; return;
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case 0x04000214: IF[1] &= ~val; return;
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