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ARM ALU is done with. as well as other shit.

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This commit is contained in:
StapleButter 2016-12-03 03:10:26 +01:00
parent 844ca45055
commit ae6e9d96da
7 changed files with 606 additions and 287 deletions
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28
ARM.cpp
View File

@ -53,12 +53,20 @@ void ARM::JumpTo(u32 addr)
{ {
// pipeline shit // pipeline shit
// TODO: THUMB!! if (addr&1)
if (addr&1) printf("!!! THUMB JUMP\n"); {
addr &= ~1;
NextInstr = Read16(addr);
R[15] = addr+2;
CPSR |= 0x20;
}
else
{
addr &= ~3; addr &= ~3;
NextInstr = Read32(addr); NextInstr = Read32(addr);
R[15] = addr+4; R[15] = addr+4;
CPSR &= ~0x20;
}
} }
void ARM::RestoreCPSR() void ARM::RestoreCPSR()
@ -70,8 +78,19 @@ s32 ARM::Execute(s32 cycles)
{ {
while (cycles > 0) while (cycles > 0)
{ {
// TODO THUM SHIT ASGAFDGSUHAJISGFYAUISAGY if (CPSR & 0x20) // THUMB
{
// prefetch
CurInstr = NextInstr;
NextInstr = Read16(R[15]);
R[15] += 2;
// actually execute
u32 icode = (CurInstr >> 6);
cycles -= ARMInterpreter::THUMBInstrTable[icode](this);
}
else
{
// prefetch // prefetch
CurInstr = NextInstr; CurInstr = NextInstr;
NextInstr = Read32(R[15]); NextInstr = Read32(R[15]);
@ -93,6 +112,7 @@ s32 ARM::Execute(s32 cycles)
cycles -= 1; // 1S. todo: check cycles -= 1; // 1S. todo: check
} }
} }
}
return cycles; return cycles;
} }

347
ARMInterpreter_ALU.cpp
View File

@ -247,6 +247,296 @@ s32 A_##x##_REG_ROR_REG(ARM* cpu) \
} }
#define A_AND(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a & b; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_AND_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a & b; \
cpu->SetNZ(res & 0x80000000, \
!res); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(AND)
#define A_EOR(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a | b; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_EOR_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a ^ b; \
cpu->SetNZ(res & 0x80000000, \
!res); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(EOR)
#define A_SUB(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a - b; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_SUB_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a - b; \
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_SUB(a, b), \
OVERFLOW_SUB(a, b, res)); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(SUB)
#define A_RSB(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = b - a; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_RSB_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = b - a; \
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_SUB(b, a), \
OVERFLOW_SUB(b, a, res)); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(RSB)
#define A_ADD(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a + b; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_ADD_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a + b; \
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_ADD(a, b), \
OVERFLOW_ADD(a, b, res)); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(ADD)
#define A_ADC(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a + b + (cpu->CPSR&0x20000000 ? 1:0); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_ADC_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res_tmp = a + b; \
u32 carry = (cpu->CPSR&0x20000000 ? 1:0); \
u32 res = res_tmp + carry; \
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_ADD(a, b) | CARRY_ADD(res_tmp, carry), \
OVERFLOW_ADD(a, b, res_tmp) | OVERFLOW_ADD(res_tmp, carry, res)); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(ADC)
#define A_SBC(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a - b - (cpu->CPSR&0x20000000 ? 0:1); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_SBC_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res_tmp = a - b; \
u32 carry = (cpu->CPSR&0x20000000 ? 0:1); \
u32 res = res_tmp - carry; \
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_SUB(a, b) | CARRY_SUB(res_tmp, carry), \
OVERFLOW_SUB(a, b, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res)); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(SBC)
#define A_RSC(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = b - a - (cpu->CPSR&0x20000000 ? 0:1); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
#define A_RSC_S(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res_tmp = b - a; \
u32 carry = (cpu->CPSR&0x20000000 ? 0:1); \
u32 res = res_tmp - carry; \
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_SUB(b, a) | CARRY_SUB(res_tmp, carry), \
OVERFLOW_SUB(b, a, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res)); \
if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \
cpu->JumpTo(res); \
cpu->RestoreCPSR(); \
return C_S(2) + C_I(c) + C_N(1); \
} \
else \
{ \
cpu->R[(cpu->CurInstr>>12) & 0xF] = res; \
return C_S(1) + C_I(c); \
}
A_IMPLEMENT_ALU_OP(RSC)
#define A_TST(c) \ #define A_TST(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \ u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a & b; \ u32 res = a & b; \
@ -291,7 +581,6 @@ A_IMPLEMENT_ALU_TEST(CMP)
A_IMPLEMENT_ALU_TEST(CMN) A_IMPLEMENT_ALU_TEST(CMN)
#define A_ORR(c) \ #define A_ORR(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \ u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a | b; \ u32 res = a | b; \
@ -326,7 +615,6 @@ A_IMPLEMENT_ALU_TEST(CMN)
A_IMPLEMENT_ALU_OP(ORR) A_IMPLEMENT_ALU_OP(ORR)
#define A_MOV(c) \ #define A_MOV(c) \
if (((cpu->CurInstr>>12) & 0xF) == 15) \ if (((cpu->CurInstr>>12) & 0xF) == 15) \
{ \ { \
@ -357,7 +645,6 @@ A_IMPLEMENT_ALU_OP(ORR)
A_IMPLEMENT_ALU_OP(MOV) A_IMPLEMENT_ALU_OP(MOV)
#define A_BIC(c) \ #define A_BIC(c) \
u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \ u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
u32 res = a & ~b; \ u32 res = a & ~b; \
@ -392,7 +679,6 @@ A_IMPLEMENT_ALU_OP(MOV)
A_IMPLEMENT_ALU_OP(BIC) A_IMPLEMENT_ALU_OP(BIC)
#define A_MVN(c) \ #define A_MVN(c) \
b = ~b; \ b = ~b; \
if (((cpu->CurInstr>>12) & 0xF) == 15) \ if (((cpu->CurInstr>>12) & 0xF) == 15) \
@ -425,4 +711,57 @@ A_IMPLEMENT_ALU_OP(BIC)
A_IMPLEMENT_ALU_OP(MVN) A_IMPLEMENT_ALU_OP(MVN)
// ---- THUMB ----------------------------------
s32 T_MOV_IMM(ARM* cpu)
{
u32 b = cpu->CurInstr & 0xFF;
cpu->R[(cpu->CurInstr >> 8) & 0x7] = b;
cpu->SetNZ(0,
!b);
return C_S(1);
}
s32 T_CMP_IMM(ARM* cpu)
{
u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
u32 b = cpu->CurInstr & 0xFF;
u32 res = a - b;
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_SUB(a, b), \
OVERFLOW_SUB(a, b, res)); \
return C_S(1);
}
s32 T_ADD_IMM(ARM* cpu)
{
u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
u32 b = cpu->CurInstr & 0xFF;
u32 res = a + b;
cpu->R[(cpu->CurInstr >> 8) & 0x7] = res;
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_ADD(a, b), \
OVERFLOW_ADD(a, b, res)); \
return C_S(1);
}
s32 T_SUB_IMM(ARM* cpu)
{
u32 a = cpu->R[(cpu->CurInstr >> 8) & 0x7];
u32 b = cpu->CurInstr & 0xFF;
u32 res = a - b;
cpu->R[(cpu->CurInstr >> 8) & 0x7] = res;
cpu->SetNZCV(res & 0x80000000, \
!res, \
CARRY_SUB(a, b), \
OVERFLOW_SUB(a, b, res)); \
return C_S(1);
}
} }

162
ARMInterpreter_ALU.h
View File

@ -5,121 +5,61 @@
namespace ARMInterpreter namespace ARMInterpreter
{ {
s32 A_TST_IMM(ARM* cpu); #define A_PROTO_ALU_OP(x) \
s32 A_TST_REG_LSL_IMM(ARM* cpu); \
s32 A_TST_REG_LSR_IMM(ARM* cpu); s32 A_##x##_IMM(ARM* cpu); \
s32 A_TST_REG_ASR_IMM(ARM* cpu); s32 A_##x##_REG_LSL_IMM(ARM* cpu); \
s32 A_TST_REG_ROR_IMM(ARM* cpu); s32 A_##x##_REG_LSR_IMM(ARM* cpu); \
s32 A_TST_REG_LSL_REG(ARM* cpu); s32 A_##x##_REG_ASR_IMM(ARM* cpu); \
s32 A_TST_REG_LSR_REG(ARM* cpu); s32 A_##x##_REG_ROR_IMM(ARM* cpu); \
s32 A_TST_REG_ASR_REG(ARM* cpu); s32 A_##x##_REG_LSL_REG(ARM* cpu); \
s32 A_TST_REG_ROR_REG(ARM* cpu); s32 A_##x##_REG_LSR_REG(ARM* cpu); \
s32 A_##x##_REG_ASR_REG(ARM* cpu); \
s32 A_##x##_REG_ROR_REG(ARM* cpu); \
s32 A_##x##_IMM_S(ARM* cpu); \
s32 A_##x##_REG_LSL_IMM_S(ARM* cpu); \
s32 A_##x##_REG_LSR_IMM_S(ARM* cpu); \
s32 A_##x##_REG_ASR_IMM_S(ARM* cpu); \
s32 A_##x##_REG_ROR_IMM_S(ARM* cpu); \
s32 A_##x##_REG_LSL_REG_S(ARM* cpu); \
s32 A_##x##_REG_LSR_REG_S(ARM* cpu); \
s32 A_##x##_REG_ASR_REG_S(ARM* cpu); \
s32 A_##x##_REG_ROR_REG_S(ARM* cpu);
s32 A_TEQ_IMM(ARM* cpu); #define A_PROTO_ALU_TEST(x) \
s32 A_TEQ_REG_LSL_IMM(ARM* cpu); \
s32 A_TEQ_REG_LSR_IMM(ARM* cpu); s32 A_##x##_IMM(ARM* cpu); \
s32 A_TEQ_REG_ASR_IMM(ARM* cpu); s32 A_##x##_REG_LSL_IMM(ARM* cpu); \
s32 A_TEQ_REG_ROR_IMM(ARM* cpu); s32 A_##x##_REG_LSR_IMM(ARM* cpu); \
s32 A_TEQ_REG_LSL_REG(ARM* cpu); s32 A_##x##_REG_ASR_IMM(ARM* cpu); \
s32 A_TEQ_REG_LSR_REG(ARM* cpu); s32 A_##x##_REG_ROR_IMM(ARM* cpu); \
s32 A_TEQ_REG_ASR_REG(ARM* cpu); s32 A_##x##_REG_LSL_REG(ARM* cpu); \
s32 A_TEQ_REG_ROR_REG(ARM* cpu); s32 A_##x##_REG_LSR_REG(ARM* cpu); \
s32 A_##x##_REG_ASR_REG(ARM* cpu); \
s32 A_##x##_REG_ROR_REG(ARM* cpu);
s32 A_CMP_IMM(ARM* cpu); A_PROTO_ALU_OP(AND)
s32 A_CMP_REG_LSL_IMM(ARM* cpu); A_PROTO_ALU_OP(EOR)
s32 A_CMP_REG_LSR_IMM(ARM* cpu); A_PROTO_ALU_OP(SUB)
s32 A_CMP_REG_ASR_IMM(ARM* cpu); A_PROTO_ALU_OP(RSB)
s32 A_CMP_REG_ROR_IMM(ARM* cpu); A_PROTO_ALU_OP(ADD)
s32 A_CMP_REG_LSL_REG(ARM* cpu); A_PROTO_ALU_OP(ADC)
s32 A_CMP_REG_LSR_REG(ARM* cpu); A_PROTO_ALU_OP(SBC)
s32 A_CMP_REG_ASR_REG(ARM* cpu); A_PROTO_ALU_OP(RSC)
s32 A_CMP_REG_ROR_REG(ARM* cpu); A_PROTO_ALU_TEST(TST)
A_PROTO_ALU_TEST(TEQ)
A_PROTO_ALU_TEST(CMP)
A_PROTO_ALU_TEST(CMN)
A_PROTO_ALU_OP(ORR)
A_PROTO_ALU_OP(MOV)
A_PROTO_ALU_OP(BIC)
A_PROTO_ALU_OP(MVN)
s32 A_CMN_IMM(ARM* cpu);
s32 A_CMN_REG_LSL_IMM(ARM* cpu);
s32 A_CMN_REG_LSR_IMM(ARM* cpu);
s32 A_CMN_REG_ASR_IMM(ARM* cpu);
s32 A_CMN_REG_ROR_IMM(ARM* cpu);
s32 A_CMN_REG_LSL_REG(ARM* cpu);
s32 A_CMN_REG_LSR_REG(ARM* cpu);
s32 A_CMN_REG_ASR_REG(ARM* cpu);
s32 A_CMN_REG_ROR_REG(ARM* cpu);
s32 A_ORR_IMM(ARM* cpu); s32 T_MOV_IMM(ARM* cpu);
s32 A_ORR_REG_LSL_IMM(ARM* cpu); s32 T_CMP_IMM(ARM* cpu);
s32 A_ORR_REG_LSR_IMM(ARM* cpu); s32 T_ADD_IMM(ARM* cpu);
s32 A_ORR_REG_ASR_IMM(ARM* cpu); s32 T_SUB_IMM(ARM* cpu);
s32 A_ORR_REG_ROR_IMM(ARM* cpu);
s32 A_ORR_REG_LSL_REG(ARM* cpu);
s32 A_ORR_REG_LSR_REG(ARM* cpu);
s32 A_ORR_REG_ASR_REG(ARM* cpu);
s32 A_ORR_REG_ROR_REG(ARM* cpu);
s32 A_ORR_IMM_S(ARM* cpu);
s32 A_ORR_REG_LSL_IMM_S(ARM* cpu);
s32 A_ORR_REG_LSR_IMM_S(ARM* cpu);
s32 A_ORR_REG_ASR_IMM_S(ARM* cpu);
s32 A_ORR_REG_ROR_IMM_S(ARM* cpu);
s32 A_ORR_REG_LSL_REG_S(ARM* cpu);
s32 A_ORR_REG_LSR_REG_S(ARM* cpu);
s32 A_ORR_REG_ASR_REG_S(ARM* cpu);
s32 A_ORR_REG_ROR_REG_S(ARM* cpu);
s32 A_MOV_IMM(ARM* cpu);
s32 A_MOV_REG_LSL_IMM(ARM* cpu);
s32 A_MOV_REG_LSR_IMM(ARM* cpu);
s32 A_MOV_REG_ASR_IMM(ARM* cpu);
s32 A_MOV_REG_ROR_IMM(ARM* cpu);
s32 A_MOV_REG_LSL_REG(ARM* cpu);
s32 A_MOV_REG_LSR_REG(ARM* cpu);
s32 A_MOV_REG_ASR_REG(ARM* cpu);
s32 A_MOV_REG_ROR_REG(ARM* cpu);
s32 A_MOV_IMM_S(ARM* cpu);
s32 A_MOV_REG_LSL_IMM_S(ARM* cpu);
s32 A_MOV_REG_LSR_IMM_S(ARM* cpu);
s32 A_MOV_REG_ASR_IMM_S(ARM* cpu);
s32 A_MOV_REG_ROR_IMM_S(ARM* cpu);
s32 A_MOV_REG_LSL_REG_S(ARM* cpu);
s32 A_MOV_REG_LSR_REG_S(ARM* cpu);
s32 A_MOV_REG_ASR_REG_S(ARM* cpu);
s32 A_MOV_REG_ROR_REG_S(ARM* cpu);
s32 A_BIC_IMM(ARM* cpu);
s32 A_BIC_REG_LSL_IMM(ARM* cpu);
s32 A_BIC_REG_LSR_IMM(ARM* cpu);
s32 A_BIC_REG_ASR_IMM(ARM* cpu);
s32 A_BIC_REG_ROR_IMM(ARM* cpu);
s32 A_BIC_REG_LSL_REG(ARM* cpu);
s32 A_BIC_REG_LSR_REG(ARM* cpu);
s32 A_BIC_REG_ASR_REG(ARM* cpu);
s32 A_BIC_REG_ROR_REG(ARM* cpu);
s32 A_BIC_IMM_S(ARM* cpu);
s32 A_BIC_REG_LSL_IMM_S(ARM* cpu);
s32 A_BIC_REG_LSR_IMM_S(ARM* cpu);
s32 A_BIC_REG_ASR_IMM_S(ARM* cpu);
s32 A_BIC_REG_ROR_IMM_S(ARM* cpu);
s32 A_BIC_REG_LSL_REG_S(ARM* cpu);
s32 A_BIC_REG_LSR_REG_S(ARM* cpu);
s32 A_BIC_REG_ASR_REG_S(ARM* cpu);
s32 A_BIC_REG_ROR_REG_S(ARM* cpu);
s32 A_MVN_IMM(ARM* cpu);
s32 A_MVN_REG_LSL_IMM(ARM* cpu);
s32 A_MVN_REG_LSR_IMM(ARM* cpu);
s32 A_MVN_REG_ASR_IMM(ARM* cpu);
s32 A_MVN_REG_ROR_IMM(ARM* cpu);
s32 A_MVN_REG_LSL_REG(ARM* cpu);
s32 A_MVN_REG_LSR_REG(ARM* cpu);
s32 A_MVN_REG_ASR_REG(ARM* cpu);
s32 A_MVN_REG_ROR_REG(ARM* cpu);
s32 A_MVN_IMM_S(ARM* cpu);
s32 A_MVN_REG_LSL_IMM_S(ARM* cpu);
s32 A_MVN_REG_LSR_IMM_S(ARM* cpu);
s32 A_MVN_REG_ASR_IMM_S(ARM* cpu);
s32 A_MVN_REG_ROR_IMM_S(ARM* cpu);
s32 A_MVN_REG_LSL_REG_S(ARM* cpu);
s32 A_MVN_REG_LSR_REG_S(ARM* cpu);
s32 A_MVN_REG_ASR_REG_S(ARM* cpu);
s32 A_MVN_REG_ROR_REG_S(ARM* cpu);
} }

15
ARMInterpreter_Branch.cpp
View File

@ -33,5 +33,20 @@ s32 A_BLX_IMM(ARM* cpu)
} }
s32 T_BCOND(ARM* cpu)
{
if (cpu->CheckCondition((cpu->CurInstr >> 8) & 0xF))
{
s32 offset = (s32)(cpu->CurInstr << 24) >> 23;
cpu->JumpTo(cpu->R[15] + offset + 1);
return C_S(2) + C_N(1);
}
else
return C_S(1);
}
} }

2
ARMInterpreter_Branch.h
View File

@ -8,6 +8,8 @@ namespace ARMInterpreter
s32 A_B(ARM* cpu); s32 A_B(ARM* cpu);
s32 A_BL(ARM* cpu); s32 A_BL(ARM* cpu);
s32 T_BCOND(ARM* cpu);
} }
#endif #endif

284
ARM_InstrTable.h
View File

@ -2,98 +2,98 @@
INSTRFUNC_PROTO(ARMInstrTable[4096]) = INSTRFUNC_PROTO(ARMInstrTable[4096]) =
{ {
// 0000 0000 0000 // 0000 0000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_REG_LSL_IMM, A_AND_REG_LSL_REG, A_AND_REG_LSR_IMM, A_AND_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_REG_ASR_IMM, A_AND_REG_ASR_REG, A_AND_REG_ROR_IMM, A_AND_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 0001 0000 // 0000 0001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_REG_LSL_IMM_S, A_AND_REG_LSL_REG_S, A_AND_REG_LSR_IMM_S, A_AND_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_REG_ASR_IMM_S, A_AND_REG_ASR_REG_S, A_AND_REG_ROR_IMM_S, A_AND_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 0010 0000 // 0000 0010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_REG_LSL_IMM, A_EOR_REG_LSL_REG, A_EOR_REG_LSR_IMM, A_EOR_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_REG_ASR_IMM, A_EOR_REG_ASR_REG, A_EOR_REG_ROR_IMM, A_EOR_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 0011 0000 // 0000 0011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_REG_LSL_IMM_S, A_EOR_REG_LSL_REG_S, A_EOR_REG_LSR_IMM_S, A_EOR_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_REG_ASR_IMM_S, A_EOR_REG_ASR_REG_S, A_EOR_REG_ROR_IMM_S, A_EOR_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 0100 0000 // 0000 0100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_REG_LSL_IMM, A_SUB_REG_LSL_REG, A_SUB_REG_LSR_IMM, A_SUB_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_REG_ASR_IMM, A_SUB_REG_ASR_REG, A_SUB_REG_ROR_IMM, A_SUB_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 0101 0000 // 0000 0101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_REG_LSL_IMM_S, A_SUB_REG_LSL_REG_S, A_SUB_REG_LSR_IMM_S, A_SUB_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_REG_ASR_IMM_S, A_SUB_REG_ASR_REG_S, A_SUB_REG_ROR_IMM_S, A_SUB_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 0110 0000 // 0000 0110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_REG_LSL_IMM, A_RSB_REG_LSL_REG, A_RSB_REG_LSR_IMM, A_RSB_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_REG_ASR_IMM, A_RSB_REG_ASR_REG, A_RSB_REG_ROR_IMM, A_RSB_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 0111 0000 // 0000 0111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_REG_LSL_IMM_S, A_RSB_REG_LSL_REG_S, A_RSB_REG_LSR_IMM_S, A_RSB_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_REG_ASR_IMM_S, A_RSB_REG_ASR_REG_S, A_RSB_REG_ROR_IMM_S, A_RSB_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1000 0000 // 0000 1000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_REG_LSL_IMM, A_ADD_REG_LSL_REG, A_ADD_REG_LSR_IMM, A_ADD_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_REG_ASR_IMM, A_ADD_REG_ASR_REG, A_ADD_REG_ROR_IMM, A_ADD_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1001 0000 // 0000 1001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_REG_LSL_IMM_S, A_ADD_REG_LSL_REG_S, A_ADD_REG_LSR_IMM_S, A_ADD_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_REG_ASR_IMM_S, A_ADD_REG_ASR_REG_S, A_ADD_REG_ROR_IMM_S, A_ADD_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1010 0000 // 0000 1010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_REG_LSL_IMM, A_ADC_REG_LSL_REG, A_ADC_REG_LSR_IMM, A_ADC_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_REG_ASR_IMM, A_ADC_REG_ASR_REG, A_ADC_REG_ROR_IMM, A_ADC_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1011 0000 // 0000 1011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_REG_LSL_IMM_S, A_ADC_REG_LSL_REG_S, A_ADC_REG_LSR_IMM_S, A_ADC_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_REG_ASR_IMM_S, A_ADC_REG_ASR_REG_S, A_ADC_REG_ROR_IMM_S, A_ADC_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1100 0000 // 0000 1100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_REG_LSL_IMM, A_SBC_REG_LSL_REG, A_SBC_REG_LSR_IMM, A_SBC_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_REG_ASR_IMM, A_SBC_REG_ASR_REG, A_SBC_REG_ROR_IMM, A_SBC_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1101 0000 // 0000 1101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_REG_LSL_IMM_S, A_SBC_REG_LSL_REG_S, A_SBC_REG_LSR_IMM_S, A_SBC_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_REG_ASR_IMM_S, A_SBC_REG_ASR_REG_S, A_SBC_REG_ROR_IMM_S, A_SBC_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1110 0000 // 0000 1110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_REG_LSL_IMM, A_RSC_REG_LSL_REG, A_RSC_REG_LSR_IMM, A_RSC_REG_LSR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_REG_ASR_IMM, A_RSC_REG_ASR_REG, A_RSC_REG_ROR_IMM, A_RSC_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
// 0000 1111 0000 // 0000 1111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_REG_LSL_IMM_S, A_RSC_REG_LSL_REG_S, A_RSC_REG_LSR_IMM_S, A_RSC_REG_LSR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_REG_ASR_IMM_S, A_RSC_REG_ASR_REG_S, A_RSC_REG_ROR_IMM_S, A_RSC_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK,
@ -198,100 +198,100 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0010 0000 0000 // 0010 0000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM, A_AND_IMM, A_AND_IMM, A_AND_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM, A_AND_IMM, A_AND_IMM, A_AND_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM, A_AND_IMM, A_AND_IMM, A_AND_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM, A_AND_IMM, A_AND_IMM, A_AND_IMM,
// 0010 0001 0000 // 0010 0001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S, A_AND_IMM_S,
// 0010 0010 0000 // 0010 0010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM, A_EOR_IMM,
// 0010 0011 0000 // 0010 0011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S, A_EOR_IMM_S,
// 0010 0100 0000 // 0010 0100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM, A_SUB_IMM,
// 0010 0101 0000 // 0010 0101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S, A_SUB_IMM_S,
// 0010 0110 0000 // 0010 0110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM, A_RSB_IMM,
// 0010 0111 0000 // 0010 0111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S, A_RSB_IMM_S,
// 0010 1000 0000 // 0010 1000 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM, A_ADD_IMM,
// 0010 1001 0000 // 0010 1001 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S, A_ADD_IMM_S,
// 0010 1010 0000 // 0010 1010 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM, A_ADC_IMM,
// 0010 1011 0000 // 0010 1011 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S, A_ADC_IMM_S,
// 0010 1100 0000 // 0010 1100 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM, A_SBC_IMM,
// 0010 1101 0000 // 0010 1101 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S, A_SBC_IMM_S,
// 0010 1110 0000 // 0010 1110 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM, A_RSC_IMM,
// 0010 1111 0000 // 0010 1111 0000
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S,
A_UNK, A_UNK, A_UNK, A_UNK, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S, A_RSC_IMM_S,
@ -1619,52 +1619,52 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK,
// 0010 0000 00 // 0010 0000 00
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
// 0010 0100 00 // 0010 0100 00
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM, T_MOV_IMM,
// 0010 1000 00 // 0010 1000 00
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
// 0010 1100 00 // 0010 1100 00
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM, T_CMP_IMM,
// 0011 0000 00 // 0011 0000 00
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
// 0011 0100 00 // 0011 0100 00
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM, T_ADD_IMM,
// 0011 1000 00 // 0011 1000 00
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
// 0011 1100 00 // 0011 1100 00
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
T_UNK, T_UNK, T_UNK, T_UNK, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM, T_SUB_IMM,
@ -1889,26 +1889,26 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK,
// 1101 0000 00 // 1101 0000 00
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
// 1101 0100 00 // 1101 0100 00
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
// 1101 1000 00 // 1101 1000 00
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
// 1101 1100 00 // 1101 1100 00
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_BCOND, T_BCOND, T_BCOND, T_BCOND,
T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK, T_UNK,

17
melonDS.depend
View File

@ -13,7 +13,7 @@
"NDS.h" "NDS.h"
"ARM.h" "ARM.h"
1480726419 source:c:\documents\sources\melonds\arm.cpp 1480729196 source:c:\documents\sources\melonds\arm.cpp
<stdio.h> <stdio.h>
"NDS.h" "NDS.h"
"ARM.h" "ARM.h"
@ -23,13 +23,13 @@
"types.h" "types.h"
"NDS.h" "NDS.h"
1480724917 c:\documents\sources\melonds\arm_instrtable.h 1480730990 c:\documents\sources\melonds\arm_instrtable.h
1480725698 c:\documents\sources\melonds\arminterpreter.h 1480725698 c:\documents\sources\melonds\arminterpreter.h
"types.h" "types.h"
"ARM.h" "ARM.h"
1480724944 source:c:\documents\sources\melonds\arminterpreter.cpp 1480727235 source:c:\documents\sources\melonds\arminterpreter.cpp
<stdio.h> <stdio.h>
"NDS.h" "NDS.h"
"ARMInterpreter.h" "ARMInterpreter.h"
@ -38,15 +38,18 @@
"ARMInterpreter_LoadStore.h" "ARMInterpreter_LoadStore.h"
"ARM_InstrTable.h" "ARM_InstrTable.h"
1480008608 c:\documents\sources\melonds\arminterpreter_branch.h 1480728965 c:\documents\sources\melonds\arminterpreter_branch.h
1480018773 source:c:\documents\sources\melonds\arminterpreter_branch.cpp 1480729161 source:c:\documents\sources\melonds\arminterpreter_branch.cpp
"ARM.h" "ARM.h"
1480028448 c:\documents\sources\melonds\arminterpreter_alu.h 1480730181 c:\documents\sources\melonds\arminterpreter_alu.h
1480028805 source:c:\documents\sources\melonds\arminterpreter_alu.cpp 1480730662 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
"ARM.h" "ARM.h"
1480724026 c:\documents\sources\melonds\arminterpreter_loadstore.h 1480724026 c:\documents\sources\melonds\arminterpreter_loadstore.h
1480725413 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
"ARM.h"