mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-24 06:39:58 -06:00
christ. CodeBlocks is retarded.
also, lots of crap. I lost track of it.
This commit is contained in:
StapleButter
@ -16,6 +16,7 @@
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include "ARM.h"
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@ -34,12 +35,12 @@ namespace ARMInterpreter
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x <<= s;
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#define LSR_IMM(x, s) \
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if (s == 0) s = 32; \
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x >>= s;
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if (s == 0) x = 0; \
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else x >>= s;
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#define ASR_IMM(x, s) \
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if (s == 0) s = 32; \
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x = ((s32)x) >> s;
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if (s == 0) x = ((s32)x) >> 31; \
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else x = ((s32)x) >> s;
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#define ROR_IMM(x, s) \
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if (s == 0) \
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@ -59,20 +60,29 @@ namespace ARMInterpreter
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}
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#define LSR_IMM_S(x, s) \
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if (s == 0) s = 32; \
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cpu->SetC(x & (1<<(s-1))); \
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x >>= s;
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if (s == 0) { \
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cpu->SetC(x & (1<<31)); \
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x = 0; \
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} else { \
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cpu->SetC(x & (1<<(s-1))); \
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x >>= s; \
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}
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#define ASR_IMM_S(x, s) \
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if (s == 0) s = 32; \
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cpu->SetC(x & (1<<(s-1))); \
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x = ((s32)x) >> s;
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if (s == 0) { \
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cpu->SetC(x & (1<<31)); \
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x = ((s32)x) >> 31; \
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} else { \
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cpu->SetC(x & (1<<(s-1))); \
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x = ((s32)x) >> s; \
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}
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#define ROR_IMM_S(x, s) \
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if (s == 0) \
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{ \
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cpu->SetC(x & 1); \
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u32 newc = (x & 1); \
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x = (x >> 1) | ((cpu->CPSR & 0x20000000) << 2); \
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cpu->SetC(newc); \
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} \
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else \
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{ \
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@ -81,32 +91,35 @@ namespace ARMInterpreter
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}
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#define LSL_REG(x, s) \
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x <<= s;
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if (s > 31) x = 0; \
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else x <<= s;
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#define LSR_REG(x, s) \
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x >>= s;
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if (s > 31) x = 0; \
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else x >>= s;
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#define ASR_REG(x, s) \
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x = ((s32)x) >> s;
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if (s > 31) x = ((s32)x) >> 31; \
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else x = ((s32)x) >> s;
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#define ROR_REG(x, s) \
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x = ROR(x, s);
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x = ROR(x, (s&0x1F));
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#define LSL_REG_S(x, s) \
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if (s > 0) cpu->SetC(x & (1<<(32-s))); \
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x <<= s;
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if (s > 31) { cpu->SetC(x & (1<<0)); x = 0; } \
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else if (s > 0) { cpu->SetC(x & (1<<(32-s))); x <<= s; }
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#define LSR_REG_S(x, s) \
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if (s > 0) cpu->SetC(x & (1<<(s-1))); \
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x >>= s;
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if (s > 31) { cpu->SetC(x & (1<<31)); x = 0; } \
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else if (s > 0) { cpu->SetC(x & (1<<(s-1))); x >>= s; }
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#define ASR_REG_S(x, s) \
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if (s > 0) cpu->SetC(x & (1<<(s-1))); \
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x = ((s32)x) >> s;
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if (s > 31) { cpu->SetC(x & (1<<31)); x = ((s32)x) >> 31; } \
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else if (s > 0) { cpu->SetC(x & (1<<(s-1))); x = ((s32)x) >> s; }
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#define ROR_REG_S(x, s) \
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if (s > 0) cpu->SetC(x & (1<<(s-1))); \
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x = ROR(x, s);
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x = ROR(x, (s&0x1F));
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@ -120,6 +133,7 @@ namespace ARMInterpreter
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#define A_CALC_OP2_REG_SHIFT_REG(shiftop) \
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u32 b = cpu->R[cpu->CurInstr&0xF]; \
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if ((cpu->CurInstr&0xF)==15) b += 4; \
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shiftop(b, cpu->R[(cpu->CurInstr>>8)&0xF]);
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@ -300,7 +314,7 @@ A_IMPLEMENT_ALU_OP(AND)
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#define A_EOR(c) \
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u32 a = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 res = a | b; \
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u32 res = a ^ b; \
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if (((cpu->CurInstr>>12) & 0xF) == 15) \
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{ \
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cpu->JumpTo(res); \
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@ -494,7 +508,7 @@ A_IMPLEMENT_ALU_OP(ADC)
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u32 res = res_tmp - carry; \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CARRY_SUB(a, b) | CARRY_SUB(res_tmp, carry), \
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CARRY_SUB(a, b) & CARRY_SUB(res_tmp, carry), \
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OVERFLOW_SUB(a, b, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res)); \
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if (((cpu->CurInstr>>12) & 0xF) == 15) \
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{ \
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@ -531,7 +545,7 @@ A_IMPLEMENT_ALU_OP(SBC)
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u32 res = res_tmp - carry; \
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cpu->SetNZCV(res & 0x80000000, \
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!res, \
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CARRY_SUB(b, a) | CARRY_SUB(res_tmp, carry), \
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CARRY_SUB(b, a) & CARRY_SUB(res_tmp, carry), \
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OVERFLOW_SUB(b, a, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res)); \
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if (((cpu->CurInstr>>12) & 0xF) == 15) \
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{ \
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@ -718,6 +732,163 @@ A_IMPLEMENT_ALU_OP(MVN)
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s32 A_MUL(ARM* cpu)
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{
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u32 rm = cpu->R[cpu->CurInstr & 0xF];
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u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
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u32 res = rm * rs;
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cpu->R[(cpu->CurInstr >> 16) & 0xF] = res;
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if (cpu->CurInstr & (1<<20))
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{
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cpu->SetNZ(res & 0x80000000,
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!res);
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if (cpu->Num==1) cpu->SetC(0);
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}
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u32 cycles;
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if ((rs & 0xFFFFFF00) == 0x00000000 || (rs & 0xFFFFFF00) == 0xFFFFFF00) cycles = 1;
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else if ((rs & 0xFFFF0000) == 0x00000000 || (rs & 0xFFFF0000) == 0xFFFF0000) cycles = 2;
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else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 3;
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else cycles = 4;
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return C_S(1) + C_I(cycles);
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}
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s32 A_MLA(ARM* cpu)
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{
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u32 rm = cpu->R[cpu->CurInstr & 0xF];
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u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
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u32 rn = cpu->R[(cpu->CurInstr >> 12) & 0xF];
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u32 res = (rm * rs) + rn;
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cpu->R[(cpu->CurInstr >> 16) & 0xF] = res;
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if (cpu->CurInstr & (1<<20))
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{
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cpu->SetNZ(res & 0x80000000,
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!res);
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if (cpu->Num==1) cpu->SetC(0);
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}
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u32 cycles;
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if ((rs & 0xFFFFFF00) == 0x00000000 || (rs & 0xFFFFFF00) == 0xFFFFFF00) cycles = 2;
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else if ((rs & 0xFFFF0000) == 0x00000000 || (rs & 0xFFFF0000) == 0xFFFF0000) cycles = 3;
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else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 4;
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else cycles = 5;
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return C_S(1) + C_I(cycles);
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}
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s32 A_UMULL(ARM* cpu)
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{
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u32 rm = cpu->R[cpu->CurInstr & 0xF];
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u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
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u64 res = (u64)rm * (u64)rs;
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cpu->R[(cpu->CurInstr >> 12) & 0xF] = (u32)res;
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cpu->R[(cpu->CurInstr >> 16) & 0xF] = (u32)(res >> 32ULL);
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if (cpu->CurInstr & (1<<20))
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{
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cpu->SetNZ((u32)(res >> 63ULL),
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!res);
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if (cpu->Num==1) cpu->SetC(0);
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}
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u32 cycles;
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if ((rs & 0xFFFFFF00) == 0x00000000) cycles = 2;
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else if ((rs & 0xFFFF0000) == 0x00000000) cycles = 3;
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else if ((rs & 0xFF000000) == 0x00000000) cycles = 4;
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else cycles = 5;
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return C_S(1) + C_I(cycles);
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}
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s32 A_UMLAL(ARM* cpu)
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{
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u32 rm = cpu->R[cpu->CurInstr & 0xF];
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u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
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u64 res = (u64)rm * (u64)rs;
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u64 rd = (u64)cpu->R[(cpu->CurInstr >> 12) & 0xF] | ((u64)cpu->R[(cpu->CurInstr >> 16) & 0xF] << 32ULL);
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res += rd;
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cpu->R[(cpu->CurInstr >> 12) & 0xF] = (u32)res;
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cpu->R[(cpu->CurInstr >> 16) & 0xF] = (u32)(res >> 32ULL);
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if (cpu->CurInstr & (1<<20))
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{
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cpu->SetNZ((u32)(res >> 63ULL),
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!res);
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if (cpu->Num==1) cpu->SetC(0);
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}
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u32 cycles;
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if ((rs & 0xFFFFFF00) == 0x00000000) cycles = 2;
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else if ((rs & 0xFFFF0000) == 0x00000000) cycles = 3;
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else if ((rs & 0xFF000000) == 0x00000000) cycles = 4;
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else cycles = 5;
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return C_S(1) + C_I(cycles);
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}
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s32 A_SMULL(ARM* cpu)
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{
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u32 rm = cpu->R[cpu->CurInstr & 0xF];
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u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
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s64 res = (s64)(s32)rm * (s64)(s32)rs;
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cpu->R[(cpu->CurInstr >> 12) & 0xF] = (u32)res;
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cpu->R[(cpu->CurInstr >> 16) & 0xF] = (u32)(res >> 32ULL);
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if (cpu->CurInstr & (1<<20))
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{
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cpu->SetNZ((u32)(res >> 63ULL),
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!res);
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if (cpu->Num==1) cpu->SetC(0);
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}
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u32 cycles;
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if ((rs & 0xFFFFFF00) == 0x00000000 || (rs & 0xFFFFFF00) == 0xFFFFFF00) cycles = 2;
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else if ((rs & 0xFFFF0000) == 0x00000000 || (rs & 0xFFFF0000) == 0xFFFF0000) cycles = 3;
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else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 4;
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else cycles = 5;
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return C_S(1) + C_I(cycles);
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}
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s32 A_SMLAL(ARM* cpu)
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{
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u32 rm = cpu->R[cpu->CurInstr & 0xF];
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u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
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s64 res = (s64)(s32)rm * (s64)(s32)rs;
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s64 rd = (s64)((u64)cpu->R[(cpu->CurInstr >> 12) & 0xF] | ((u64)cpu->R[(cpu->CurInstr >> 16) & 0xF] << 32ULL));
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res += rd;
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cpu->R[(cpu->CurInstr >> 12) & 0xF] = (u32)res;
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cpu->R[(cpu->CurInstr >> 16) & 0xF] = (u32)(res >> 32ULL);
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if (cpu->CurInstr & (1<<20))
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{
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cpu->SetNZ((u32)(res >> 63ULL),
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!res);
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if (cpu->Num==1) cpu->SetC(0);
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}
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u32 cycles;
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if ((rs & 0xFFFFFF00) == 0x00000000 || (rs & 0xFFFFFF00) == 0xFFFFFF00) cycles = 2;
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else if ((rs & 0xFFFF0000) == 0x00000000 || (rs & 0xFFFF0000) == 0xFFFF0000) cycles = 3;
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else if ((rs & 0xFF000000) == 0x00000000 || (rs & 0xFF000000) == 0xFF000000) cycles = 4;
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else cycles = 5;
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return C_S(1) + C_I(cycles);
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}
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s32 A_CLZ(ARM* cpu)
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{
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// TODO: ARM9 only
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@ -962,7 +1133,7 @@ s32 T_SBC_REG(ARM* cpu)
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cpu->R[cpu->CurInstr & 0x7] = res;
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cpu->SetNZCV(res & 0x80000000,
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!res,
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CARRY_SUB(a, b) | CARRY_SUB(res_tmp, carry),
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CARRY_SUB(a, b) & CARRY_SUB(res_tmp, carry),
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OVERFLOW_SUB(a, b, res_tmp) | OVERFLOW_SUB(res_tmp, carry, res));
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return C_S(1);
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}
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